Bei Yu
Professor
Applies machine learning and deep learning to electronic design automation and computer vision.
Bei Yu's lab at CUHK works on accelerators, chips & architecture. 353 papers since 2023. 41 PhD students and 2 master's students. 32 alumni, most often to Huawei and Adobe. Applications close .
At a glance
- papers, 2023–2026
- 92/ year
- at T1 venues
- 0%
- PhD students
- 41
- MS students
- 2
- alumni listed
- 32
Papers by yearfrom the lab homepage, 2023–2026
- 133 papers2026 · T1 0 · collecting
- 95 papers2025 · T1 0
- 69 papers2024 · T1 0
- 56 papers2023 · T1 0
T1 venuesOther
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture11 papers
- electronic design1 paper
- design automation1 paper
- applies machine0 papers
- applies0 papers
Paper list
From the lab homepage.
2026133 papers
- 08-12A Multi-Granularity Retrieval Augmented Generation Framework for EDA Tasks Leveraging Knowledge Graph
- 139:1-139:26Accelet: Hardware-software Co-design of Chiplet-based DNN Accelerators (opens in a new tab)
- 08-12AMigration: Analog placement Migration via Adaptive Constraints Relaxation
- 6-11AnalogVerifier: A Neuro-Symbolic Framework for Analog Circuit Verification (opens in a new tab)
- Association for Computational Linguistics (ACL), San Diego, July 2-7Analytical FFN-to-MoE Restructuring via Activation Pattern Analysis (opens in a new tab)
- 691-704Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR Metrics (opens in a new tab)
- 19-22BEAM: Bidirectional MEEF-Driven Mask Optimization for Curvilinear Photonic Design (opens in a new tab)
- 6-13Beyond Data Scaling: Representation-Centric Pre-training for Vision-Language-Action Models
- 6-11Beyond Majority Voting: Self-Reflective Test-Time Reinforcement Learning for LLM Reasoning (opens in a new tab)
- 6-13Bias-Variance Optimized Preference Optimization for Large Reasoning Models
- 2548-2562Bounded Dynamic Level Maintenance for Efficient Logic Optimization (opens in a new tab)
- 26-29BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs (opens in a new tab)
202595 papers
- 22-253D-Flow: Flow-based Standard Cell Legalization for 3D ICs (opens in a new tab)
- 08-10A Hybrid Optimization Framework for Power-Efficient Pulsed Latch Utilization in Clock Networks (opens in a new tab)
- —A Learned Performance Model with Transfer Learning Across GPUs on Tensorized Instructions (opens in a new tab)
- 22-25A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis (opens in a new tab)
- 4341-4354Adaptive ILT via Multi-level Lithography Simulation (opens in a new tab)
- 402-415Analytical Heterogeneous Die-to-Die 3D Placement with Macros (opens in a new tab)
- 1394-1405BAQE: Backend-Adaptive DNN Deployment via Synchronous Bayesian Quantization and Hardware Configuration Exploration (opens in a new tab)
- 22Behavioral Fingerprinting of Large Language Models (opens in a new tab)
- 54:1-54:20Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling (opens in a new tab)
- 13-19Bridging Layout and RTL: Knowledge Distillation based Timing Prediction (opens in a new tab)
- 1180-1192Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits (opens in a new tab)
- 26-30ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs (opens in a new tab)
202469 papers
- 53:1-53:25A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs (opens in a new tab)
- 2674-2686AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for Via Layers (opens in a new tab)
- 27-31An Agile Framework for Efficient LLM Accelerator Development and Model Inference (opens in a new tab)
- 1624-1637Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration (opens in a new tab)
- 21-27BetterV: Controlled Verilog Generation with Discriminative Guidance (opens in a new tab)
- 21-27BiE: Bi-Exponent Block Floating-Point for Large Language Models Quantization (opens in a new tab)
- 1-23BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration (opens in a new tab)
- 23-27CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning (opens in a new tab)
- 25-27CBTune: Contextual Bandit Tuning for Logic Synthesis (opens in a new tab)
- 3184-3197ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (opens in a new tab)
- 23-27ChatPattern: Layout Pattern Customization via Natural Language (opens in a new tab)
- 17-21Classes Are Not Equal: An Empirical Study on Image Recognition Fairness (opens in a new tab)
202356 papers
- 594-605A GPU-enabled Level Set Method for Mask Optimization (opens in a new tab)
- 3210-3223A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU (opens in a new tab)
- 1199-1211A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation (opens in a new tab)
- 1372-1387Adaptive Perspective Distillation for Semantic Segmentation (opens in a new tab)
- 5006-5019Aging-aware Critical Path Selection via Graph Attention Networks (opens in a new tab)
- 04-08ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs (opens in a new tab)
- 02AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search (opens in a new tab)
- 01ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis (opens in a new tab)
- 06-10ATFormer: A Learned Performance Model with Transfer Learning Across Devices for Large-Scale Transformers (opens in a new tab)
- 7-14AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution (opens in a new tab)
- International Symposium of EDA (ISEDA), May 9-11Bit-Level Quantization for Efficient Layout Hotspot Detection (opens in a new tab)
- 17-19BOMIG: A Majority Logic Synthesis Framework for AQFP Logic (opens in a new tab)
Where alumni went32 listed, 40% to industry
Industry 12Academia 18
Most often to
- Huawei
- Adobe
- ByteDance
Also to
- CUHK
- HKUST
- Carnegie Mellon University
Apply to CUHKFall 2027
Computer Science and Engineering MPhil/PhD
- Round
- HKPFS / main round
- Opens
- —
- GRE
- See program page
- English
- Interview in English
- Fee
- See program page
Not yet confirmed for this intake.
Similar labsnearest by research summary
- USUIUC
Daniel Kang
- Efficient training & inference
- SGNTU
Yawei Li
- Accelerators, chips & architecture
- USUC Berkeley
Joseph Gonzalez
- Efficient training & inference
- SGNTU
Yonggang Wen
- Efficient training & inference
- CHETH Zurich
Yannis Chronis
- Accelerators, chips & architecture
- USUIUC
Fan Lai
- Efficient training & inference
Your notes
Save this lab to keep notes.
Data
Some numbers could not be verified:
- The lab site and the paper record do not agree.
- Collected
- Verified
- Papers
- The lab homepage
- Members
- Lab homepage
- Alumni
- Lab homepage
Tiers are venue classifications, not lab rankings.
CUHKcloses