Evangeline F. Y. Young
Professor
Works on CAD of VLSI circuits, combinatorial optimization and machine learning for physical design.
Evangeline F. Y. Young's lab at CUHK works on accelerators, chips & architecture and learning theory & optimization. 51 papers since 2023, 11 at top venues, mostly DAC and ICCAD. 11 PhD students. 45 alumni, most often to Huawei and Alibaba. Applications close .
At a glance
- papers, 2023–2026
- 13/ year
- at T1 venues
- 22%
- PhD students
- 11
- MS students
- 0
- alumni listed
- 45
Papers by yearfrom DBLP, 2023–2026
- 9 papers2026 · T1 0 · collecting
- 10 papers2025 · T1 3
- 21 papers2024 · T1 6
- 11 papers2023 · T1 2
T1 venuesOtherVenues: DAC, ICCAD
Research focuspaper titles that use each topic's words
- Learning theory & optimization9 papers
- Accelerators, chips & architecture5 papers
- cad0 papers
- combinatorial optimization0 papers
- vlsi0 papers
Paper list
From DBLP.
20269 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.An Open-Source High-Concurrency and High-Performance Parallel Router for UltraScale FPGAs (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.Efficient and Effective E-graph-based Logic Optimization (opens in a new tab)
- ISPDGradient-Guided RC Weighting for Timing-Driven Global Routing (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.InstantGR: Scalable GPU Parallelization for 3-D Global Routing (opens in a new tab)
- ACM Trans. Reconfigurable Technol. Syst.Introduction to the Special Issue on Open Source Tools for Reconfigurable Devices and Systems (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.MALT: ML Assisted Shallow-Light Tree Construction (opens in a new tab)
- FPGARND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Simulation-Based Combinational Equivalence Checking With Multiple GPUs (opens in a new tab)
- J. Hardw. Syst. Secur.TroLLoc: Security Closure against Hardware Trojans by Logic Locking and Layout Hardening (opens in a new tab)
202510 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Unified Parallel Framework for LUT Mapping and Logic Optimization (opens in a new tab)
- MLCADDr. Guide: AI-Guided Detailed Routing (opens in a new tab)
- ICCAD (T1)ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping (opens in a new tab)
- DATEFast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention (opens in a new tab)
- ISPDInvited: AI-assisted Routing (opens in a new tab)
- KSEMPOAgent: A Multi-agent Controller Towards Adaptive Parameter Optimization (opens in a new tab)
- DAC (T1)Simulation-based Parallel Sweeping: A New Perspective on Combinational Equivalence Checking (opens in a new tab)
- DAC (T1)SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding (opens in a new tab)
- IACR Trans. Cryptogr. Hardw. Embed. Syst.Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort (opens in a new tab)
- FPLTRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer (opens in a new tab)
202421 papers
- ACM Great Lakes Symposium on VLSIA Multi-agent Generative Model for Collaborative Global Routing Refinement (opens in a new tab)
- FCCMA Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints (opens in a new tab)
- ISPDAccelerating Physical Design from 1 to N (opens in a new tab)
- ACM Great Lakes Symposium on VLSIAn Open-Source Fast Parallel Routing Approach for Commercial FPGAs (opens in a new tab)
- ACM Great Lakes Symposium on VLSIControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation (opens in a new tab)
- ASPDACCoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs (opens in a new tab)
- ACM Great Lakes Symposium on VLSIDynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing (opens in a new tab)
- Sci. China Inf. Sci.Erratum to: Large circuit models: opportunities and challenges (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement (opens in a new tab)
- ASPDACFineMap: A Fine-grained GPU-parallel LUT Mapping Engine (opens in a new tab)
- DAC (T1)GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis (opens in a new tab)
- ICCAD (T1)Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration (opens in a new tab)
202311 papers
- ASP-DACAn Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems (opens in a new tab)
- ACM Great Lakes Symposium on VLSICPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems (opens in a new tab)
- DAC (T1)EDGE: Efficient DAG-based Global Routing Engine (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning (opens in a new tab)
- ISPDFastPass: Fast Pin Access Analysis with Incremental SAT Solving (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.GAMER: GPU-Accelerated Maze Routing (opens in a new tab)
- ISPDGPU Acceleration in Physical Synthesis (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning (opens in a new tab)
- DAC (T1)Rethinking AIG Resynthesis in Parallel (opens in a new tab)
- ISPDSecurity Closure of IC Layouts Against Hardware Trojans (opens in a new tab)
- ACM Great Lakes Symposium on VLSISPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems (opens in a new tab)
Where alumni went45 listed, 50% to industry
Industry 10Academia 10
Most often to
- Huawei
- Alibaba
- IBM
Also to
- CUHK
- UIUC
- Cornell University
Apply to CUHKFall 2027
Computer Science and Engineering MPhil/PhD
- Round
- HKPFS / main round
- Opens
- —
- GRE
- See program page
- English
- Interview in English
- Fee
- See program page
Not yet confirmed for this intake.
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