CNShanghai Jiao Tong UniversitySchool of Integrated Circuits (Information and Electronic Engineering)
Guanghui He
教授
Works on energy-efficient circuits, wireless baseband chips, real-time image processing and DNN hardware.
Guanghui He's lab at SJTU works on accelerators, chips & architecture, efficient training & inference and rendering & appearance. 63 papers since 2023, 11 at top venues, mostly DAC and ISCA. Applications close .
At a glance
- papers, 2023–2026
- 16/ year
- at T1 venues
- 17%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 12 papers2026 · T1 3 · collecting
- 20 papers2025 · T1 3
- 17 papers2024 · T1 2
- 14 papers2023 · T1 3
T1 venuesOtherVenues: DAC, ISCA, Expert Systems with Applications, ICASSP, ICCAD
Research focuspaper titles that use each topic's words
- Efficient training & inference19 papers
- Accelerators, chips & architecture9 papers
- dnn3 papers
- Rendering & appearance1 paper
- circuits0 papers
Paper list
From DBLP.
202612 papers
- CICCA 51.19 mm2, 4 TB/s bandwidth 3D Logic-on-SRAM Stacking CGRA Chip (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.A Full-Digital Heterogeneous Computing-in-Memory With Dual-Bit Serialized Weight Stream and Ping-Pong Computing for Efficient Transformer Acceleration (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.A Heterogeneous CIM Architecture With Splittable Nonvolatile Computing-in-SRAM Cell Pairs Enabling Efficient On-Chip Neural Network Inference (opens in a new tab)
- ISCA (T1)Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs (opens in a new tab)
- ISITADMM Decoding of Quantum LDPC Codes (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations (opens in a new tab)
- Neural Comput. Appl.Deep learning for stereo image super-resolution: a comprehensive survey (opens in a new tab)
- ISCA (T1)Efficient 3D Gaussian Splatting with Axis-Shared Rasterization and Order-independent Transmittance (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.HiRe: A Hierarchical Reconfigurable Architecture for Large-Scale Multichiplet DNN Accelerators (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Layout Synthesis of RRAM Array With Minimized Proximity Effect (opens in a new tab)
- ISCA (T1)MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems (opens in a new tab)
- IEEE Trans. ComputersSD-Acc: Accelerating Stable Diffusion through Phase-Aware Sampling and Hardware Co-Optimizations (opens in a new tab)
202520 papers
- IEEE J. Emerg. Sel. Topics Circuits Syst.Adaptive Two-Range Quantization and Hardware Co-Design for Large Language Model Acceleration (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.An Efficient Multi-View Cross-Attention Accelerator for Vision-Centric 3D Perception in Autonomous Driving (opens in a new tab)
- DAC (T1)BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.COSA Plus: Enhanced Co-Operative Systolic Arrays for Attention Mechanism in Transformers (opens in a new tab)
- IEEE Trans. ComputersDESA: Dataflow Efficient Systolic Array for Acceleration of Transformers (opens in a new tab)
- NeurocomputingDiffusion models for image super-resolution: State-of-the-art and future directions (opens in a new tab)
- IEEE J. Emerg. Sel. Topics Circuits Syst.Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System (opens in a new tab)
- IEEE J. Emerg. Sel. Topics Circuits Syst.Efficient Hardware Architecture Design for Rotary Position Embedding of Large Language Models (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.HyCTor: A Hybrid CNN-Transformer Network Accelerator With Flexible Weight/Output Stationary Dataflow and Multicore Extension (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems (opens in a new tab)
- DAC (T1)KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference (opens in a new tab)
- Signal Image Video Process.Lightweight image super-resolution based on mixer-based focal modulation network (opens in a new tab)
202417 papers
- IEEE Trans. Circuits Syst. II Express BriefsA Broad-Spectrum and High-Throughput Compression Engine for Neural Network Processors (opens in a new tab)
- ISCASA High-Throughput Lossless Image Compression Engine Optimized for Compression Ratio (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Precision-Scalable Deep Neural Network Accelerator With Activation Sparsity Exploitation (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.BSViT: A Bit-Serial Vision Transformer Accelerator Exploiting Dynamic Patch and Weight Bit-Group Quantization (opens in a new tab)
- IEEE Trans. ComputersCoDA: A Co-Design Framework for Versatile and Efficient Attention Accelerators (opens in a new tab)
- DAC (T1)DEFA: Efficient Deformable Attention Acceleration via Pruning-Assisted Grid-Sampling and Multi-Scale Parallel Processing (opens in a new tab)
- IEEE Trans. Computational ImagingDTDeMo: A Deep Learning-Based Two-Stage Image Demosaicing Model With Interpolation and Enhancement (opens in a new tab)
- Appl. Soft Comput.Efficient image super-resolution based on transformer with bidirectional interaction (opens in a new tab)
- Sci. China Inf. Sci.Hardware-oriented algorithms for softmax and layer normalization of large language models (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators (opens in a new tab)
- Eng. Appl. Artif. Intell.Lightweight image super-resolution network based on extended convolution mixer (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture (opens in a new tab)
202314 papers
- CVPR WorkshopA Simple Transformer-style Network for Lightweight Image Super-resolution (opens in a new tab)
- ISSCCCCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition (opens in a new tab)
- DAC (T1)COSA:Co-Operative Systolic Arrays for Multi-head Attention Mechanism in Neural Network using Hybrid Data Reuse and Fusion Methodologies (opens in a new tab)
- DAC (T1)FLNA: An Energy-Efficient Point Cloud Feature Learning Accelerator with Dataflow Decoupling (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.GEM: A Generalized Memristor Device Modeling Framework Based on Neural Network for Transient Circuit Simulation (opens in a new tab)
- Neural NetworksLightweight image super-resolution based multi-order gated aggregation network (opens in a new tab)
- Inf. FusionLightweight image super-resolution based on deep learning: State-of-the-art and future directions (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsLow-Complexity Precision-Scalable Multiply-Accumulate Unit Architectures for Deep Neural Network Accelerators (opens in a new tab)
- CVPR WorkshopMixer-based Local Residual Network for Lightweight Image Super-resolution (opens in a new tab)
- ASICONMUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5 (opens in a new tab)
- CVPR WorkshopNTIRE 2023 Challenge on Image Super-Resolution (×4): Methods and Results (opens in a new tab)
- CVPR WorkshopNTIRE 2023 Challenge on Stereo Image Super-Resolution: Methods and Results (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
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- Self-funded
- Opens
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- GRE
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- English
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