Deming Chen
Professor
Studies hardware-software co-design, including FPGA and high-level synthesis for efficient deep learning accelerators.
Deming Chen's lab at UIUC works on accelerators, chips & architecture, efficient training & inference and speech synthesis & voice. 45 papers since 2023, 15 at top venues, mostly DAC and NeurIPS. 13 PhD students and 10 master's students. 56 alumni, most often to NVIDIA and Apple. Applications close .
At a glance
- papers, 2023–2026
- 12/ year
- at T1 venues
- 33%
- PhD students
- 13
- MS students
- 10
- alumni listed
- 56
Papers by yearfrom the lab homepage, 2023–2026
- 0 papers2026 · T1 0 · collecting
- 9 papers2025 · T1 3
- 22 papers2024 · T1 5
- 14 papers2023 · T1 7
T1 venuesOtherVenues: DAC, NeurIPS, ICCAD, ASPLOS, ICCV
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture11 papers
- Speech synthesis & voice5 papers
- high-level5 papers
- high-level synthesis5 papers
- Efficient training & inference4 papers
Paper list
From the lab homepage.
20259 papers
- ICCAD (T1)Invited Paper: Hardware-Software Co-Design for Highly Optimized, Customized, and Reliable AI Systems
- NeurIPS (T1)LLM Strategic Reasoning: Agentic Study through Behavioral Game Theory
- IEEE Transactions on ComputersMLCD: Machine Learning-based Code Version and Device Selection for Heterogeneous Systems
- Proceedings of IEEE International Conference on LLM-Aided DesignOpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
- Proceedings of ACM/IEEE Great Lakes Symposium on VLSIPREFACE: A Reinforcement Learning Framework for Code Verification via LLM Prompt Repair
- Proceedings of Semiconductor Research Corporation (SRC) TECHCONProof2Silicon: Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learning
- MICRO (T1)StreamTensor: Make Tensors Stream in Dataflow Accelerators for LLMs
- Proceedings of Semiconductor Research Corporation (SRC) TECHCONToward A Multi-Agent LLM Framework for Automated Microprocessor Hardware Design
- ESORICSVeriFLo: Verifiable Provenance with Fault Localization for Inter-domain Routing
202422 papers
- Proceedings of the SC'24 Workshops of the International Conference on High Performance Computing, Network, Storage, and AnalysisAcceleration of Graph Neural Networks with Heterogenous Accelerators Architecture
- LADAn Exploratory Study of using LLM to Detect Credit Card Fraud
- LADAn Iteratively-refined Dataset for High-Level Synthesis Functional Verification through LLM-Aided Bug Injection
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsAutoAI2C: An Automated Hardware Generator for DNN Acceleration on both FPGA and ASIC
- ACM Transactions on Reconfigurable Technology and SystemsCHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture
- Embedded Machine Learning for Cyber-Physical, IoT, and Edge ComputingCompilation and Optimizations for Efficient Machine Learning on Embedded Systems
- NeurIPS (T1)Decision-Making Behavior Evaluation Framework for LLMs under Uncertain Context
- Proceedings of EAI International Conference on Security and Privacy in Communication NetworksDPU-LARK: DPU-Leveraged Attestation of Remote Kernels for Security of OT Networks
- Proceedings of IEEE International Conference on Communications (ICC): IoT and Sensor Networks SymposiumFedCore: Straggler-Free Federated Learning with Distributed Coresets
- ASPLOS (T1)HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
- Proceedings of IEEE/ACM Asia and South Pacific Design Automation ConferenceHomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN
- DAC (T1)Invited: New Solutions on LLM Acceleration, Optimization, and Application
202314 papers
- DAC (T1)AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators
- ACM Transactions on Reconfigurable Technology and SystemsAutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis
- Proceedings of Semiconductor Research Corporation (SRC) TECHCONBest Presenter Award
- Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate ArraysCHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
- —Cybersecurity for Modern Smart Grid against Emerging Threats (opens in a new tab)
- ICML WorkshopEH-DNAS: End-to-End Hardware-aware Differentiable Neural Architecture Search
- ICCV (T1)Extensible and Efficient Proxy for NAS
- Proceedings of the International Conference on Field-Programmable Logic and ApplicationsFSSD: FPGA-based Emulator for SSDs
- Proceedings of International Symposium on Physical DesignHigh-level Synthesis for Domain Specific Computing
- DAC (T1)Lightning Talk: The Next Wave of High-level Synthesis
- ISCA (T1)Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization
- SOSP (T1)RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design
Where alumni went56 listed, 86% to industry
Industry 37Academia 6
Most often to
- NVIDIA
- Apple
Also to
- law school
- Georgia Tech
- Institute of Computer Science
Apply to UIUCFall 2027
UIUC Siebel Computer Science PhD
- Round
- Single round
- Opens
- —
- GRE
- optional
- English
- TOEFL iBT / IELTS
- Fee
- USD 90
Not yet confirmed for this intake.
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