Zeke Wang
ZJU100 Young Professor
Builds heterogeneous computing platforms with FPGAs, P4 switches and GPUs for large deep-learning model training, graph neural network systems, cloud infrastructure and privacy computing.
Zeke Wang's lab at Zhejiang works on distributed, cloud & edge systems, accelerators, chips & architecture and graph learning. 33 papers since 2023, 17 at top venues, mostly ICDE and EuroSys. Applications close .
At a glance
- papers, 2023–2026
- 9/ year
- at T1 venues
- 52%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 7 papers2026 · T1 4 · collecting
- 10 papers2025 · T1 5
- 4 papers2024 · T1 2
- 12 papers2023 · T1 6
T1 venuesOtherVenues: ICDE, EuroSys, HPCA, ISCA, ASPLOS
Research focuspaper titles that use each topic's words
- Graph learning6 papers
- Distributed, cloud & edge systems4 papers
- Accelerators, chips & architecture2 papers
- fpgas2 papers
- heterogeneous computing0 papers
Paper list
From the lab homepage.
20267 papers
- ASPLOS (T1)BAT: Efficient Generative Recommender Serving with Bipartite Attention
- ISCA (T1)DisDP: Disaggregating Compute, Network, and Storage for Model-Sharded Data-Parallel Training
- SIGMOD (T1)FlashANNS: GPU-Driven I/O Pipelining for Eliminating Storage–Compute Bottlenecks in Billion-Scale Similarity Search
- SCP4FP: Enabling Practical In-network Floating-point AllReduce via SmartNIC-SmartSwitch Co-design
- EuroSys (T1)SmartNS: Enabling Line-rate and Flexible Network Stack with SmartNIC
- SCSmartReduce: SmartSwitch-Aware SmartNIC-Centric Sparse AllReduce
- TONSwCC-Sec: Secure Software-Programmable and Per-Packet Congestion Control in RDMA Engine
202510 papers
- ICDE (T1)CAM: Asynchronous GPU-Initiated, CPU-Managed SSD Management for Batching Storage Access
- ICLR (T1)DeFT: Decoding with Flash Tree-attention for Efficient Tree-structured LLM Inference
- SCDHAP: Towards Efficient OLAP in a Disaggregated and Heterogeneous Environment
- TONHare: A Systematic Framework for Efficient and Generally Automatic Hotspot Offloading on Programmable Switches
- PPoPPHelios: Efficient Distributed Dynamic Graph Sampling for Online GNN Inference
- ICDE (T1)Hyperion: Optimizing SSD Access is All You Need to Enable Cost-efficient Out-of-core GNN Training
- SCMoment: Co-optimizing Physical Communication Topology and Data Placement for Multi-GPU Out-of-core GNN.(Best Student Paper Nomination)
- ICDE (T1)Ratel: Optimizing Holistic Data Movement to Fine-tune 100B Model on a Consumer GPU
- HPCA (T1)RpcNIC: Enabling Efficient Datacenter RPC Offloading on PCIe-attached SmartNICs
- ATCSwCC: Software-Programmable and Per-Packet Congestion Control in RDMA Engine
20244 papers
- ICNPDemystifying Datapath Accelerator Enhanced Off-path SmartNIC
- ICDE (T1)DmRPC: Disaggregated Memory-aware Datacenter RPC for Data-intensive Applications
- SCTorchGT: A Holistic System for Large-scale Graph Transformer Training
- NSDI (T1)Understanding Routable PCIe Performance for Composable Infrastructures
202312 papers
- TCADA Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators
- SIGCOMM (T1)Achelous: Enabling Programmability, Elasticity, and Reliability in Hyperscale Cloud Networks
- HPCA (T1)BM-Store: A Transparent and High-performance Local Storage Architecture for Bare-metal Clouds Enabling Large-scale Deployment
- TPDSCritique of “productivity, Portability, Performance: Data-Centric Python” by SCC Team From Zhejiang University
- EuroSys (T1)Dynamic Graph Sampling Service for Real-time GNN Inference at Scale. (Best Poster Award)
- DAC (T1)Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
- ATCLegion: Automatically Pushing the Envelope of Multi-GPU System for Billion-Scale GNN Training
- TPDSP4SGD: Programmable Switch Enhanced Model-Parallel Training on Generalized Linear Models on Distributed FPGAs
- ISCA (T1)SmartDS: Middle-Tier-centric SmartNIC Enabling Application-aware Message Split for Disaggregated Block Storage
- TCADSparseACC: A Generalized Linear Model Accelerator for Sparse Datasets
- FPTSSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs
- TNNLS (T1)Staleness-reduction Mini-batch K-means
Where alumni went
Alumni are not listed on the lab homepage.
Apply to ZhejiangFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- Per ZJU language requirements
- Fee
- RMB 800
Not yet confirmed for this intake.
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Data
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- The member list could not be found on the lab site.
- The alumni list could not be found on the lab site.
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