Jieru Zhao
Tenured Track Associate Professor
Works on intelligent computing systems, compilation and heterogeneous computing for AI models.
Jieru Zhao's lab at SJTU works in AI Systems & Hardware. 33 papers since 2023, 22 at top venues, mostly DAC and ASPLOS. 6 PhD students and 7 master's students. 6 alumni, most often to Alibaba and Baidu. Applications close .
At a glance
- papers, 2023–2026
- 9/ year
- at T1 venues
- 67%
- PhD students
- 6
- MS students
- 7
- alumni listed
- 6
Papers by yearfrom the lab homepage, 2023–2026
- 10 papers2026 · T1 9 · collecting
- 7 papers2025 · T1 6
- 10 papers2024 · T1 4
- 6 papers2023 · T1 3
T1 venuesOtherVenues: DAC, ASPLOS, HPCA, ICLR, ISCA
Research focuspaper titles that use each topic's words
- heterogeneous4 papers
- compilation0 papers
- heterogeneous computing0 papers
- intelligent computing0 papers
- computing systems0 papers
Paper list
From the lab homepage.
202610 papers
- ISCA (T1)CODO: An Automated Compiler for Comprehensive Dataflow Optimization
- MICRO (T1)DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction
- OSDI (T1)ECHO: Efficient KV Cache Offloading with Lossless Prefetching for Serving Native Sparse Attention LLMs
- ICLR (T1)Flash-Mono: Feed-Forward Accelerated Gaussian Splatting Monocular SLAM
- ICLR (T1)FreeKV: Boosting KV Cache Retrieval for Efficient LLM Inference
- MICRO (T1)Keleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlations
- ICML (T1)Learning High-Frequency Continuous Action Chunks in Latent Space
- DAC (T1)LiveVLM: Efficient Online Video Understanding via Streaming-Oriented KV Cache and Retrieval
- ASPLOS (T1)Nebula: Enable City-Scale 3D Gaussian Splatting in Virtual Reality via Collaborative Rendering and Accelerated Stereo Rasterization
- TACONPUMeter: Automatic Operator Optimization for Ascend NPU with Accurate Analytical Performance Models
20257 papers
- DAC (T1)ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
- NeurIPS (T1)Communication-Efficient Diffusion Denoising Parallelization via Reuse-then-Predict Mechanism
- SCDHAP: Towards Efficient OLAP in a Disaggregated and Heterogeneous Environment
- ICCAD (T1)HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGA
- HPCA (T1)RpcNIC: Enabling Efficient Datacenter RPC Offloading on PCIe-attached SmartNICs
- ASPLOS (T1)StreamGrid: Streaming Point Cloud Analytics via Compulsory Splitting and Deterministic Termination
- DAC (T1)StreamingGS: Voxel-Based Streaming 3D Gaussian Splatting with Memory Optimization and Architectural Support
202410 papers
- ISCA (T1)A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things
- TCADAMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA
- HPCA (T1)An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
- TCADAutomatic Mapping of Heterogeneous DNN Models on Adaptive Multi-Accelerator Systems
- ICCDAutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
- ASPLOS (T1)DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflows
- TRETSFADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs
- TCADHardware-Software Co-Design Enabling Static and Dynamic Sparse Attention Mechanisms
- DATEHierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
- ECCV (T1)O2V-Mapping: Online Open-Vocabulary Mapping with Neural Implicit Representation
20236 papers
- ICRA (T1)FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow
- TCADHL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
- DAC (T1)MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
- ICSPreference-Aware Co-location Scheduling on Heterogeneous NUMA Architectures To Improve Resource Utilization
- HotOSSkadi: Building a Distributed Runtime for Data Systems in Disaggregated Data Centers
- DAC (T1)SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication
Where alumni went6 listed, 100% to industry
Industry 4Academia 0
Most often to
- Alibaba
- Baidu
- ByteDance
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
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