Hongyang Jia
Assistant Professor
Works on emerging computing technologies for VLSI, including approximate computing and compute-in-memory accelerators.
Hongyang Jia's lab at Tsinghua works on accelerators, chips & architecture. 31 papers since 2023, 4 at top venues, mostly DAC and ICLR. Applications close .
At a glance
- papers, 2023–2026
- 8/ year
- at T1 venues
- 13%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 8 papers2026 · T1 2 · collecting
- 10 papers2025 · T1 1
- 9 papers2024 · T1 1
- 4 papers2023 · T1 0
T1 venuesOtherVenues: DAC, ICLR, ISCA, MLSys
Research focuspaper titles that use each topic's words
- compute-in-memory8 papers
- Accelerators, chips & architecture7 papers
- approximate computing0 papers
- vlsi0 papers
- emerging0 papers
Paper list
From DBLP.
20268 papers
- IEEE Trans. Circuits Syst. I Regul. Pap.A 28-nm Versatile TinyML SoC With Flexible Hetero-Fabric Dataflow Orchestration and Compute/Storage-Density-Adjustable CIM (opens in a new tab)
- IEEE J. Solid State CircuitsA Compact Energy-Efficient Unified Micro-Robotic Processor With Flexible Visual Perception (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA High-SNR SRAM-LUT-Based In-Memory-Computing Macro Supporting Energy-Efficient INT8 and FP8 Computation (opens in a new tab)
- IEEE J. Solid State CircuitsAn Area-Efficient Lookup-Table -Based eDRAM Digital CIM Macro for Neural Network Inference (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.BVDT: A 28-nm LUT-Assisted Transformer Accelerator With Basis-Vector Compression and Decomposed Computing (opens in a new tab)
- ICLR (T1)Scalable and Adaptive Trust-Region Learning via Projection Convex Hull (opens in a new tab)
- ASP-DACScope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators (opens in a new tab)
- ISCA (T1)SHyLA: 3D-Stacked NVM-DRAM Hybrid LLM-Inference Architecture Exploiting Data and Memory Heterogeneity (opens in a new tab)
202510 papers
- CICCA 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC (opens in a new tab)
- IEEE J. Solid State CircuitsA Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference (opens in a new tab)
- IEEE J. Solid State CircuitsEnabling Energy-Efficient Homomorphic Encryption Evaluation via eDRAM-Based In-Situ Computing in an Edge Processor (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference (opens in a new tab)
- IEEE J. Solid State CircuitsHybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS (opens in a new tab)
- MLSys (T1)HyC-LoRA: Memory Efficient LoRA Fine-tuning with Hybrid Activation Compression (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.MCHEAS: Optimizing Large-Parameter NTT Over Multicluster In-Situ FHE Accelerating System (opens in a new tab)
- HCSPresto: A Unified RISC-V-Compatible SoC for Multi-Scheme FHE Acceleration over Module Lattice (opens in a new tab)
- CICCPro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution (opens in a new tab)
20249 papers
- ISSCC34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing (opens in a new tab)
- VLSI Technology and CircuitsA 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-Assisted Cores (opens in a new tab)
- CICCA 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA Heterogeneous Microprocessor for Intermittent AI Inference Using Nonvolatile-SRAM-Based Compute-In-Memory (opens in a new tab)
- A-SSCCA Unified Microrobotic Visual-Perception Processor with 62.2-FPS/mm2 and 103-uJ/frame Navigation in 28nm (opens in a new tab)
- IEEE J. Solid State CircuitsCramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS (opens in a new tab)
- DATEESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration (opens in a new tab)
- SOCCExploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the Edge (opens in a new tab)
- DAC (T1)Invited: Automatic Hardware/Software Design for High-Speed Autonomous Unmanned Aerial Vehicles Guided by a Flight Model (opens in a new tab)
20234 papers
- ISSCCA 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsAn RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree (opens in a new tab)
- Proc. IEEEData-Driven Security and Stability Rule in High Renewable Penetrated Power System Operation (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to TsinghuaFall 2027
Computer Science PhD (international applicants)
- Round
- Main
- Opens
- GRE
- See program page
- English
- Per school catalog
- Fee
- RMB 800
Not yet confirmed for this intake.
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