George Constantinides
Professor of Digital Computation
Studies finite-precision arithmetic and automated hardware design, often for efficient machine learning acceleration.
George Constantinides's lab at Imperial works on accelerators, chips & architecture and efficient training & inference. 42 papers since 2023, 6 at top venues, mostly DAC and EMNLP. 5 PhD students. 41 alumni, most often to Apple and CEO and Co-Founder at muse.ai. Applications close .
At a glance
- papers, 2023–2026
- 11/ year
- at T1 venues
- 14%
- PhD students
- 5
- MS students
- 0
- alumni listed
- 41
Papers by yearfrom DBLP, 2023–2026
- 5 papers2026 · T1 0 · collecting
- 12 papers2025 · T1 2
- 8 papers2024 · T1 1
- 17 papers2023 · T1 3
T1 venuesOtherVenues: DAC, EMNLP, Findings of EMNLP, HPCA, ICLR
Research focuspaper titles that use each topic's words
- Efficient training & inference8 papers
- Accelerators, chips & architecture5 papers
- acceleration3 papers
- learning acceleration1 paper
- efficient machine0 papers
Paper list
From DBLP.
20265 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting (opens in a new tab)
- IEEE Trans. ComputersBit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization (opens in a new tab)
- HEARTHigh Performance Multi-Processor Systems on FPGA (opens in a new tab)
- ACM Trans. Reconfigurable Technol. Syst.hls4ml: A Flexible, Open Source Platform for Deep Learning Acceleration on Reconfigurable Hardware (opens in a new tab)
- DATETowards Input-Distribution-Aware Approximate Multiplier Generation for CNNs (opens in a new tab)
202512 papers
- EuroMLSysAMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks (opens in a new tab)
- FCCMBanked Memories for Soft SIMT Processors (opens in a new tab)
- HPCA (T1)BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Constraint-Aware E-Graph Rewriting for Hardware Performance Optimization (opens in a new tab)
- FPGAGreater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT (opens in a new tab)
- FCCMNeuraLUT-Assemble: Hardware-Aware Assembling of Sub-Neural Networks for Efficient LUT Inference (opens in a new tab)
- ASAPPermuting Accumulation Order for Low-Precision Machine Learning (opens in a new tab)
- FCCMPh.D. Project Hardware-Aware Neural Networks (opens in a new tab)
- IEEE Trans. ComputersPolyLUT: Ultra-Low Latency Polynomial Inference With Hardware-Aware Structured Pruning (opens in a new tab)
- ICLR (T1)QERA: an Analytical Framework for Quantization Error Reconstruction (opens in a new tab)
- FPGAReducedLUT: Table Decomposition with "Don't Care" Conditions (opens in a new tab)
- Findings of EMNLPTraining with Fewer Bits: Unlocking Edge LLMs Training with Stochastic Rounding (opens in a new tab)
20248 papers
- FPGAA Statically and Dynamically Scalable Soft GPGPU (opens in a new tab)
- FUZZINGAutomated Feature Testing of Verilog Parsers using Fuzzing (Registered Report) (opens in a new tab)
- ARITHCombining Power and Arithmetic Optimization via Datapath Rewriting (opens in a new tab)
- FPLExploring FPGA designs for MX and beyond (opens in a new tab)
- ICML (T1)LQER: Low-Rank Quantization Error Reconstruction for LLMs (opens in a new tab)
- FPLNeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.ROVER: RTL Optimization via Verified E-Graph Rewriting (opens in a new tab)
- HEARTSoft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap (opens in a new tab)
202317 papers
- DSN-WA Parametrizable Template for Approximate Logic Synthesis (opens in a new tab)
- FCCMATHEENA: A Toolflow for Hardware Early-Exit Network Automation (opens in a new tab)
- DAC (T1)Automating Constraint-Aware Datapath Optimization using E-Graphs (opens in a new tab)
- IEEE Trans. ComputersBalancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets (opens in a new tab)
- SOAP@PLDICombining E-Graphs with Abstract Interpretation (opens in a new tab)
- FMCADDatapath Verification via Word-Level E-Graph Rewriting (opens in a new tab)
- FPLeGPU: A 750 MHz Class Soft GPGPU for FPGA (opens in a new tab)
- ACM Trans. Embed. Comput. Syst.Enabling Binary Neural Network Training on the Edge (opens in a new tab)
- CFErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing (opens in a new tab)
- ICFPTFPGA Resource-aware Structured Pruning for Real-Time Neural Networks (opens in a new tab)
- TAC (T1)Horizon-Independent Preconditioner Design for Linear Predictive Control (opens in a new tab)
- ACM Trans. Reconfigurable Technol. Syst.Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks (opens in a new tab)
Where alumni went41 listed, 72% to industry
Industry 23Academia 9
Most often to
- Apple
- CEO and Co-Founder at muse.ai
- Chief Executive Officer at truid.ai
Also to
- Imperial College London
- Institute of Computing Technology
- Mahanakorn University of Technology
Apply to Imperial2027 (Apr/Oct)
Computing PhD
- Round
- Round 2 (1 Dec 2026)
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- none
Confirmed on the program page.
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