Nam Sung Kim
Professor
Studies computer architecture and systems for AI, including energy-efficient processor, memory and network architectures for machine learning.
Nam Sung Kim's lab at UIUC works on accelerators, chips & architecture and efficient training & inference. 83 papers since 2023, 40 at top venues, mostly MICRO and ISCA. 18 PhD students and 7 master's students. 22 alumni. Applications close .
At a glance
- papers, 2023–2026
- 22/ year
- at T1 venues
- 48%
- PhD students
- 18
- MS students
- 7
- alumni listed
- 22
Papers by yearfrom the lab homepage, 2023–2026
- 27 papers2026 · T1 12 · collecting
- 25 papers2025 · T1 13
- 16 papers2024 · T1 9
- 15 papers2023 · T1 6
T1 venuesOtherVenues: MICRO, ISCA, HPCA, ASPLOS, DAC
Research focuspaper titles that use each topic's words
- Efficient training & inference12 papers
- Accelerators, chips & architecture7 papers
- processor2 papers
- network architectures0 papers
- computer architecture0 papers
Paper list
From the lab homepage.
202627 papers
- CALA Simulator for LLM inference systems exploiting CXL memory pools
- MICRO (T1)AMG: AMX-GPU cooperative acceleration of billion-scale ANNS via GEMM reformulation
- MICRO (T1)ARC: adaptive reconfigurable CXL hotness monitoring
- SOSP (T1)Borges: A low-latency distributed shared log on a CXL memory/SSD hybrid
- CALCapacity-latency tradeoffs in CXL memory expander at hyperscale
- CALCharacterizing system-level trade-offs of Intel DSA for user-space IPC offloading
- IEEE Transactions on Circuits and Systems I: Regular PapersCharacterizing the intrinsic bank-level accuracy vs. energy trade-off of SRAM-based analog in-memory computing architectures in 28 nm CMOS
- ISPASSCompiler and system optimizations for gem5 simulator
- MICRO (T1)CXL AnySSD: A composable CXL SSD using a CXL Type-2 device and any SSDs
- CALCXL-Tracer: Accurate, full-system memory tracing on commercial hardware via CXL memory
- MICRO (T1)Elastic LLM serving on FPGAs via partial reconfiguration: a case study using the Altera FPGA AI Suite
- CALHyGIN: Hybrid CPU/GPU-initiated communication for mixture-of-experts training
202525 papers
- DAC (T1)A full-system, programmable, and extensible in-memory computing simulation framework for deep learning
- ISCA (T1)A4: Microarchitecture-aware LLC management for datacenter servers with emerging I/O devices
- CALCABANA: Cluster-aware query batching for accelerating billion-scale ANNS with Intel AMX
- IEEE Computer Architecture LettersCooperative Memory Deduplication with Intel Data Streaming Accelerator (opens in a new tab)
- MICRO (T1)DRAM fault classification through large-scale field monitoring for robust memory RAS management
- ISCA (T1)Dynamic Load Balancer in Intel® Xeon® Scalable Processor: Performance analyses, enhancements, and guidelines
- TVLSIExploiting chiplet integration technology for fast high-capacity DRAM modules
- IEEE Computer Architecture LettersHardware-Accelerated Kernel-Space Memory Compression Using Intel QAT (opens in a new tab)
- CALHINT: A hardware platform for intra-host NIC traffic and SmartNIC emulation
- ISCA (T1)Hybrid SLC-MLC RRAM mixed-signal processing-in-memory architecture for Transformer acceleration via gradient redistribution
- ISPASSIntel In-Memory Analytics Accelerator: performance characterization and guidelines
- ISCA (T1)LIA: A single-GPU LLM inference acceleration with cooperative AMX-enabled CPU-GPU computation and CXL offloading
202416 papers
- ACM International Conference on Architectural Support for Programming Languages and Operating SystemsA quantitative analysis and guidelines of data streaming accelerator in modern intel xeon scalable processors (opens in a new tab)
- HPCA (T1)An lpddr-based cxl-pnm platform for tco-efficient inference of transformer-based large language models (opens in a new tab)
- ACM International Conference on Architectural Support for Programming Languages and Operating SystemsAttAcc! Unleashing the power of PIM for batched transformer-based generative model inference (opens in a new tab)
- MICRO (T1)Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective (opens in a new tab)
- ISCA (T1)DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands (opens in a new tab)
- IEEE Computer Architecture LettersExploiting Intel® Advanced Matrix Extensions (AMX) for Large Language Model Inference (opens in a new tab)
- International Conference on Parallel Architectures and Compilation TechniquesFriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks (opens in a new tab)
- ISCA (T1)Hal: Hardware-assisted load balancing for energy-efficient snic-host cooperative computing (opens in a new tab)
- NSDI (T1)Harmonic: Hardware-assisted RDMA Performance Isolation for Public Clouds
- ISCA (T1)Intel accelerators ecosystem: An soc-oriented perspective: Industry product (opens in a new tab)
- Proceedings of the Workshop on Disruptive Memory SystemsLupin: Tolerating Partial Failures in a CXL Pod (opens in a new tab)
- EuroSys (T1)Scalecache: A scalable page cache for multiple solid-state drives (opens in a new tab)
202315 papers
- ISPASSAnalyzing Energy Efficiency of a Server with a SmartNIC under SLO Constraints (opens in a new tab)
- MICRO (T1)Demystifying cxl memory with genuine cxl-ready systems and devices (opens in a new tab)
- MICRO (T1)How to kill the second bird with one ecc: The pursuit of row hammer resilient dram (opens in a new tab)
- IEEE Computer Architecture LettersLADIO: Leakage-aware direct I/O for I/O-intensive workloads (opens in a new tab)
- IISWCMaking sense of using a smartnic to reduce datacenter tax from slo and tco perspectives (opens in a new tab)
- ISCA (T1)Mesa: Microarchitecture extensions for spatial architecture generation (opens in a new tab)
- IEEE Computer Architecture LettersNohammer: Preventing row hammer with last-level cache management (opens in a new tab)
- HPCA (T1)Rambda: Rdma-driven acceleration framework for memory-intensive µs-scale datacenter applications (opens in a new tab)
- HPCA (T1)Shadow: Preventing row hammer in dram with intra-subarray row shuffling (opens in a new tab)
- MICRO (T1)Special issue on emerging system interconnects (opens in a new tab)
- USENIX Annual Technical ConferenceSTYX: Exploiting SmartNIC capability to reduce datacenter memory tax (opens in a new tab)
- HotOSTowards a Manageable Intra-Host Network (opens in a new tab)
Where alumni went22 listed
Apply to UIUCFall 2027
UIUC Siebel Computer Science PhD
- Round
- Single round
- Opens
- —
- GRE
- optional
- English
- TOEFL iBT / IELTS
- Fee
- USD 90
Not yet confirmed for this intake.
Similar labsnearest by research summary
- CNTsinghua
Youhui Zhang
- Accelerators, chips & architecture
- CNSJTU
Jianguo Yao
- Accelerators, chips & architecture
- DETUM
Erika Covi
- Accelerators, chips & architecture
- CAToronto
Andreas Moshovos
- Accelerators, chips & architecture
- CHETH Zurich
Giacomo Indiveri
- Accelerators, chips & architecture
- USGeorgia Tech
Divya Mahajan
- Distributed, cloud & edge systems
Your notes
Save this lab to keep notes.
Data
Checked against the lab homepage.
- Collected
- Verified
- Papers
- The lab homepage
- Members
- Lab homepage
- Alumni
- Lab homepage
Tiers are venue classifications, not lab rankings.
UIUCcloses