Naresh R Shanbhag
Professor
Studies energy-efficient integrated circuits for machine learning, including deep in-memory architectures for edge inference.
Naresh R Shanbhag's lab at UIUC works on accelerators, chips & architecture and efficient training & inference. 17 papers since 2023, 5 at top venues, mostly ICASSP and DAC. 65 alumni. Applications close .
At a glance
- papers, 2023–2026
- 4/ year
- at T1 venues
- 29%
- PhD students
- 0
- MS students
- 0
- alumni listed
- 65
Papers by yearfrom the lab homepage, 2023–2026
- 0 papers2026 · T1 0 · collecting
- 5 papers2025 · T1 1
- 7 papers2024 · T1 1
- 5 papers2023 · T1 3
T1 venuesOtherVenues: ICASSP, DAC, ICCAD, ICML
Research focuspaper titles that use each topic's words
- in-memory13 papers
- Accelerators, chips & architecture2 papers
- Efficient training & inference1 paper
- edge1 paper
- energy-efficient0 papers
Paper list
From the lab homepage.
20255 papers
- ESSERCA 28nm 31.2 TOPS/W diffusion transformer accelerator using memory-in-compute architecture (opens in a new tab)
- DAC (T1)A full-system, programmable, and extensible in-memory computing simulation framework for deep learning (opens in a new tab)
- TCAS-ICharacterizing the intrinsic bank-level accuracy vs. energy trade-off of SRAM-Based in-memory computing architectures in 28nm CMOS (opens in a new tab)
- TCAS-IEnergy-accuracy trade-offs in massive MIMO signal detection using SRAM-based in-memory computing (opens in a new tab)
- CICCForward error correction requirements for data center connectivity (opens in a new tab)
20247 papers
- JSSCCompute SNDR-boosted 22nm MRAM-based in-memory computing macro using statistical error compensation (opens in a new tab)
- JxCDCEnergy-accuracy trade-offs for resistive in-memory computing architectures (opens in a new tab)
- IEEE Transactions on Signal ProcessingEnhancing the accuracy of 6T SRAM-based in-memory architecture via maximum likelihood detection (opens in a new tab)
- Neural Information Processing Systems (NeurIPS) WorkshopGrowing accurate and robust neural networks on the Edge (opens in a new tab)
- ISCASMassive MIMO signal detection using SRAM-based in-memory computing (opens in a new tab)
- ICCAD (T1)On the security vulnerabilities of MRAM-based in-memory computing architectures against model extraction attacks (opens in a new tab)
- IEDMThe energy-accuracy-security trade-off in resistive in-memory architectures (opens in a new tab)
20235 papers
- ICASSP (T1)Boosting the accuracy of SRAM-based in-memory architectures via maximum likelihood-based error compensation method (opens in a new tab)
- ESSCIRCCompute SNR-boosted 22nm MRAM-based in-memory computing macro using statistical error compensation (opens in a new tab)
- ICASSP (T1)Enhancing the accuracy of resistive in-memory architectures using adaptive signal processing (opens in a new tab)
- ICML (T1)On the robustness of randomized ensembles to adversarial perturbations (opens in a new tab)
- Design Automation and Test in EuropePRIVE:Efficient RRAM programming with chip verification for RRAM-based in-memory computing acceleration (opens in a new tab)
Where alumni went65 listed
Apply to UIUCFall 2027
UIUC Siebel Computer Science PhD
- Round
- Single round
- Opens
- —
- GRE
- optional
- English
- TOEFL iBT / IELTS
- Fee
- USD 90
Not yet confirmed for this intake.
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