Xiyuan Tang
助理教授
Leads the PRIME group, researching high-performance analog/mixed-signal circuits and AI chips.
Xiyuan Tang's lab at Peking works on accelerators, chips & architecture. 59 papers since 2023. 10 PhD students. 5 alumni. Applications close .
At a glance
- papers, 2023–2026
- 15/ year
- at T1 venues
- 0%
- PhD students
- 10
- MS students
- 0
- alumni listed
- 5
Papers by yearfrom the lab homepage, 2023–2026
- 15 papers2026 · T1 0 · collecting
- 19 papers2025 · T1 0
- 13 papers2024 · T1 0
- 12 papers2023 · T1 0
T1 venuesOther
Research focuspaper titles that use each topic's words
- analog11 papers
- Accelerators, chips & architecture1 paper
- mixed-signal0 papers
- high-performance0 papers
- researching0 papers
Paper list
From the lab homepage.
202615 papers
- 3113-3124, JuneA 0.2V Edge-Pursuit Continuous-Time Ising Machine Using Ring-Oscillator Collapse and Delay-Enabled Positive Feedback (opens in a new tab)
- (*: Corresponding author)A 0.65V 13b 50MS/s Pipelined-SAR ADC with Cyclic Dynamic Amplifier and Bayesian-Based Gain Calibration (opens in a new tab)
- 1240-1253, MarchA 1131-Kb/mm2 14.0-to-53.3-TOPS/W 8-Bit Analog-Assisted Digital Compute-in-Memory With Hybrid Local-Refresh eDRAM for Attention Computing (opens in a new tab)
- (*: Corresponding author)A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration (opens in a new tab)
- —A 28-nm CIM-Based Annealing Processor with One-Shot Weight Access, Dynamic Batching, and Bubble-Less Pipeline for Large-Scale Path Planning Problems (opens in a new tab)
- (*: Corresponding author)A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability (opens in a new tab)
- —A first-principles hetero-integrated Fourier transform system based on memristors (opens in a new tab)
- (*: Corresponding author)A Multiscale Neural Interface SoC with 89.5-dB DR 4.54μW Analog Frontend and 0.00013 mm2/Ch Spatiotemporal Spike Feature Extractor (opens in a new tab)
- (*: Corresponding author)An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization (opens in a new tab)
- (*: Corresponding author)An Easy-Driving Incremental Zoom ADC With Skipped Sampling Scheme and NS-SAR Quantizer (opens in a new tab)
- —GRAIN: A Design-Intent-Driven Analog Layout Migration Framework
- —LiteDVS: A Low-Data-Redundancy Dynamic Vision Sensor with Hybrid Readout and In-Pixel Denoising
202519 papers
- 449-453, MarchA 12.6-pJ/Conversion Temperature Sensor With 0.98-mV/K Temperature-Voltage Sensitivity (opens in a new tab)
- (*: Corresponding author)A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single- Amplification-Based kT/C Noise Cancellation Technique (opens in a new tab)
- (*: Corresponding author)A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead Compensation Technique (opens in a new tab)
- —A 28nm 534.6TOPS/W Mixed-Precision Edge Accelerator for Embodied AI Using Stochastic Computing (opens in a new tab)
- (*: Corresponding author)A 4.82-uW 183.4dB-FoM SNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator (opens in a new tab)
- (+: Equal contribution; *: Corresponding author)A 617.7 TOPS/W PCM-Based Charge-Domain CIM Macro with Capacitor Reuse Method and Scalable Local Compute Unit (opens in a new tab)
- (*: Corresponding author)A Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI (opens in a new tab)
- 2520-2528, JuneA Dual Slope Boosted Relaxation Oscillator With 2.93µJ/cycle Energy Efficiency and 0.068% Period Jitter in 180nm CMOS (opens in a new tab)
- (*: Corresponding author)A High-Density eDRAM-Based Cache Featuring Enhanced Data Retention Time and Low-Power Sense Amplifier (opens in a new tab)
- (*: Corresponding author)A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference (opens in a new tab)
- 1793-1804, MayA Variation-Tolerant Continuous-Time Ising Machine with eDRAM-based Spin Interaction and Leaked Negative Feedback Annealing (opens in a new tab)
- (*: Corresponding author)Adder-DCIM: A Parallel Bit-Flexible Digital CIM Joint Model Compression Framework for AdderNet Inference (opens in a new tab)
202413 papers
- 2209-2218, JulyA 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp (opens in a new tab)
- 1706-1718, AprilA 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation (opens in a new tab)
- (*: Corresponding author)A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation (opens in a new tab)
- (*: Corresponding author)A 266 F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function with <6×10-9 Bit Error Rate Through Efficient Redundancy Strategy (opens in a new tab)
- (*: Corresponding author)}A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI (opens in a new tab)
- 842-854, MarchA 4-Bit Calibration-Free Computing-In-Memory Macro with 3T1C Current-Programmed Dynamic-Cascode Multi-Level-Cell eDRAM (opens in a new tab)
- (+: Equal contribution; *: Corresponding author)A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing (opens in a new tab)
- —CASCADE: A Framework for CNN Accelerator Synthesis with Concatenation and Refreshing Dataflow (opens in a new tab)
- —EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration (opens in a new tab)
- (+: Equal contribution; *: Corresponding author)MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks (opens in a new tab)
- —Neural Manifold Learning Based on 40 nm Dual-Mode PCM Compute-in-Memory Chip with Hardware Adaptive Drift Compensation (opens in a new tab)
- (*: Corresponding author)}PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis (opens in a new tab)
202312 papers
- (*: Corresponding author)A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer (opens in a new tab)
- —A 28-nm 38-to-102-TOPS/W 8-b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference (opens in a new tab)
- 1835-1845, MayA 28nm 16Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro (opens in a new tab)
- (*: Corresponding author)A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization (opens in a new tab)
- —A Bandwidth-Adaptive Pipelined SAR ADC with Three-Stage Cascoded Floating Inverter Amplifier (opens in a new tab)
- (*: Corresponding author)A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC (opens in a new tab)
- 2293-2305, JuneA Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC (opens in a new tab)
- —An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ∆Σ ADC with 105dB SFDR in 28-nm CMOS (opens in a new tab)
- 257-260An Energy Efficient Capacitive Sensor Readout Circuit with Zoomed Time Domain Quantization (opens in a new tab)
- 1450-1461, MayAn in-memory-computing charge-domain ternary CNN classifier (opens in a new tab)
- 145-161Design Techniques for Energy Efficient Analog-to-Digital Converters (opens in a new tab)
- (Best Paper Award Track T)SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (opens in a new tab)
Where alumni went5 listed
Apply to PekingFall 2027
Computer Science PhD (international applicants)
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