Hussam Amrouch
Professor
Designs AI processors beyond the von Neumann paradigm, including in-memory computing with emerging technologies and cryogenic circuits.
Hussam Amrouch's lab at TUM works on accelerators, chips & architecture. 128 papers since 2023, 1 at top venues, mostly Nature Communications. 32 PhD students. 7 alumni.
At a glance
- papers, 2023–2026
- 33/ year
- at T1 venues
- 1%
- PhD students
- 32
- MS students
- 0
- alumni listed
- 7
Papers by yearfrom the lab homepage, 2023–2026
- 7 papers2026 · T1 0 · collecting
- 38 papers2025 · T1 0
- 29 papers2024 · T1 0
- 54 papers2023 · T1 1
T1 venuesOtherVenues: Nature Communications
Research focuspaper titles that use each topic's words
- in-memory16 papers
- in-memory computing8 papers
- Accelerators, chips & architecture6 papers
- emerging6 papers
- processors2 papers
Paper list
From the lab homepage.
20267 papers
- Proceedings of the Conference on Design, Automation & Test in Europe (DATE'26)Challenges and Perspectives in Advanced CMOS & 5.5D Packaging: Design, Reliability and Security
- Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'26)Power Side-Channel Attacks in Nanosheet Circuits
- Proceedings of the IEEE International Reliability Physics Symposium (IRPS'26)Revealing the Impact of Parasitic Effects on CFET Reliability and Performance Across Devices, Standard Cells, and Circuits
- International Conference on Information Systems Security and Privacy (ICISSP'26)Securing Hyper-Dimensional Computing: A Locking Mechanism with FPGA Implementation
- The Fourteenth International Conference on Learning Representations (ICLR'26)Si-GT: Fast Interconnect Signal Integrity Analysis for Integrated Circuit Design via Graph Transformers
- IEEE Transactions on Electron Devices (TED)Soft Error Analysis in Nanosheet and Forksheet Transistors: From Device Physics to Circuit and Memory Impact
- IEEE Latin American Test Symposium (LATS'26)Validating Statistical Delay Test Generation under Timing Variations via SAT-Based ATPG
202538 papers
- Proceedings of the IEEE International Reliability Physics Symposium (IRPS'25)A Comprehensive Investigation of Cryogenic Aging in 28nm CMOS: Suppression of BTI and HCD in Circuits and SRAM
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC)A Comprehensive Vmin Characterization of 5 nm FinFET-based SRAM at Cryogenic Temperatures
- IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)A PUF-based Obfuscation Scheme For In-Memory Architectures
- International Symposium on Quality Electronic Design (ISQED'25)Accelerating Reliability Analysis for Aging and Self-heating using Machine Learning
- Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'25)Benchmarking Cryogenic Circuits Using 5 nm FinFETs for Quantum Processing
- Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI'25)BEOL Interconnects for 2nm Technology Node and Beyond
- IEEE International Symposium on VLSI Design, Automation and Test (VLSI-TSA'25)Beyond FinFETs: Transistor-to-GDS Benchmarking of AI Accelerators using Nanosheets and CFETs
- IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCAS-AI)Capacitor Minimization in Analog Synapses for Efficient and Compact Binarized SNNs
- IEEE Computer Society Annual Symposium on VLSI (ISVLSI'25)Carbon-Efficient 3D DNN Acceleration: Optimizing Performance and Sustainability
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC)CFET Beyond 3~nm: SRAM Reliability under Design-Time and Run-Time Variability
- IEEE Transactions on Computers (TC)Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling down to 10K in Advanced 7nm FinFETs
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC)Cryogenic Hyper-Dimensional In-Memory Computing using Ferroelectric TCAM
202429 papers
- IEEE Transactions on Electron Devices (TED)A Physics-Based Model for Oxide-Semiconductor-Based Ferroelectric Field-Effect Transistors
- Proceedings of the Conference on Design, Automation & Test in Europe (DATE)Algorithm to Technology Co-Optimization for CiM-based Hyperdimensional Computing
- IEEE Electron Devices Technology & Manufacturing Conference (EDTM'24)Benchmarking IWO-based Logic Circuits for Monolithic 3D Integration
- IEEE Transactions on Computers (TC)CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-based Caches
- The Multidisciplinary Open Access Journal IEEE Access (IEEE Access)CircuitHD: Brain-inspired Hyperdimensional Computing for Circuit Recognition
- IntegrationExploring BTI Aging Effects on Spatial Power Density and Temperature Profiles of VLSI Chips
- Advanced Intelligent SystemsFerroelectric Transistors in Monolithic 3D Integration: Reliable DNN Acceleration in the Face of Temperature
- IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability
- Proceedings of the Conference on Design, Automation & Test in Europe (DATE)HDCircuit: Brain-inspired Hyperdimensional Computing for Circuit Recognition
- in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), AprilImpact of Self-Heating in 5 nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction
- DOIIn-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies
- Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'24)Innovations in Hardware Security: Leveraging FeFET Technology for Future Opportunities
202354 papers
- DOI5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing
- DOIAccelerating FeFET Reliability Analysis using Machine Learning
- IEEE International Test Conference (ITC)Analysis and Characterization of Defects in FeFETs
- DOIApproximation-Aware and Quantization-Aware Training for Graph Neural Networks
- TEDBEOL FeFET SPICE-Compatible Model for Benchmarking 3-D Monolithic In-Memory TCAM Computation
- DOIBeyond von Neumann Era: Brain-Inspired Hyperdimensional Computing to the Rescue
- DOIChallenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits
- DOICharacterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths
- DOICompact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
- DOICompact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology
- TEDComprehensive Modeling of Switching Behavior in BEOL FeFET for Monolithic 3-D Integration
- IEEE Transactions on Electron Devices (TED)Comprehensive Modeling of Switching Behaviour in BEOL FeFET for Monolithic 3D Integration
Where alumni went7 listed
Apply to TUMRolling
Not announced yet
Computer Science Doctorate (CIT)
- Round
- Rolling (position-based)
- Opens
- —
- GRE
- See program page
- English
- Very good written and spoken English; no minimum test score
- Fee
- See program page
Confirmed on the program page.
Similar labsnearest by research summary
- USUCLA
Hanrui Wang
- Accelerators, chips & architecture
- CNPeking
Xiyuan Tang
- Accelerators, chips & architecture
- CNTsinghua
Xuehai Qian
- Accelerators, chips & architecture
- USStanford
Priyanka Raina
- Accelerators, chips & architecture
- USUW
Scott Hauck
- Accelerators, chips & architecture
- CNTsinghua
Peng Qu
- Accelerators, chips & architecture
Your notes
Save this lab to keep notes.
Data
Checked against the lab homepage.
- Collected
- Verified
- Papers
- The lab homepage
- Members
- Lab homepage
- Alumni
- Lab homepage
Tiers are venue classifications, not lab rankings.