Zhezhi He
Tenured Track Associate Professor
Works on hardware-software co-design for intelligent computing, neuromorphic computing and EDA.
Zhezhi He's lab at SJTU works on accelerators, chips & architecture. 32 papers since 2023, 13 at top venues, mostly ICCAD and DAC. 6 PhD students and 2 master's students. 5 alumni. Applications close .
At a glance
- papers, 2023–2026
- 8/ year
- at T1 venues
- 41%
- PhD students
- 6
- MS students
- 2
- alumni listed
- 5
Papers by yearfrom the lab homepage, 2023–2026
- 6 papers2026 · T1 4 · collecting
- 11 papers2025 · T1 6
- 8 papers2024 · T1 2
- 7 papers2023 · T1 1
T1 venuesOtherVenues: ICCAD, DAC, ICML, ISCA, MICRO
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture3 papers
- neuromorphic computing1 paper
- hardware-software0 papers
- hardware-software co-design0 papers
- intelligent computing0 papers
Paper list
From the lab homepage.
20266 papers
- MICRO (T1)Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference
- ISCA (T1)ELSA: An ELastic SNN Inference Architecture for Efficient Neuromorphic Computing
- ISCA (T1)NasZip: Software and Hardware Co-design to Accelerate Approximate Nearest Neighbor Search with DIMM-based Near-Data Processing
- ICCAD (T1)SASA: Sparsity-Adaptive Framework for Spiking Neural Network Acceleration on CPU
- CVPR-26Seele: A unified acceleration framework for real-time gaussian splatting
- HPCA-26Splatonic: Architecture Support for 3D Gaussian Splatting SLAM via Sparse Processing
202511 papers
- TCAD25APU: Accelerate Point Cloud Neural Networks via Unified Processing-in-SRAM Architecture
- DAC (T1)BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration
- International Symposium of EDAFinetuned Decision Transformer with Tree Search for Logic Synthesis Optimization
- Proceedings of Design, Automation and Test in Europe ConferenceHaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
- International Workshop on Logic & SynthesisHigh-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling
- ICCAD (T1)MASIM: An Energy-Efficient Multi-Array Scheduler for SIMD Logic-in-Memory Architectures
- DAC (T1)PICK: An SRAM-based Processing-in-Memory Accelerator for K-Nearest-Neighbor Search in Point Clouds
- MICRO (T1)PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference
- Proceedings of the ACM International Conference on Architectural Support for Programming Languages and Operating SystemsStreamGrid: Streaming Point Cloud Analytics via Compulsory Splitting and Deterministic Termination
- ICCAD (T1)VeriRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning
- CVPR (T1)VISTREAM: Improving Computation Efficiency of Visual Perception Streaming via Law-of-Charge-Conservation Inspired Spiking Neural Network
20248 papers
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsA Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization
- DATEAn Efficient Logic Operation Scheduler For Minimizing Memory Footprint Of In-memory SIMD Computation
- Proceedings of The European Conference on Computer Vision (ECCV)BKDSNN: Enhancing the Performance of Learning-based Spiking Neural Networks Training with Blurred Knowledge Distillation
- ICML (T1)CLLMs: Consistency Large Language Models
- ISEDAERL-LS: Accelerating the Optimization of Logic Synthesis with Evolutionary Reinforcement Learning
- ICANNObtaining Optimal Spiking Neural Network in Sequence Learning via CRNN-SNN Conversion
- DATEPIMLC: Logic Compiler for Bit-serial Based PIM
- ICML (T1)SpikeZIP-TF: Conversion is All You Need for Transformer-based SNN
20237 papers
- ICCDGIM: Versatile GNN Acceleration with Reconfigurable Processing-in-Memory
- ICCDGPT-LS: Generative Pre-Trained Transformer with Off-line Reinforcement Learning for Logic Synthesis
- ICCDHyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model
- Nature Communications (T1)Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T-4R structure for high-density memory
- Design, Automation & Test in Europe Conference & ExhibitionPIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy
- TCVSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations
- Proceedings of the on Great Lakes Symposium on VLSIXMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph
Where alumni went5 listed, 100% to industry
Industry 1Academia 0
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
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