CNShanghai Jiao Tong UniversitySchool of Integrated Circuits (Information and Electronic Engineering)
Chen Zhang
教轨助理教授
Works on multi-GPU supernode interconnects and systems for large-model training and inference.
Chen Zhang's lab at SJTU works on efficient training & inference and accelerators, chips & architecture. 30 papers since 2023, 22 at top venues, mostly DAC and ISCA. Applications close .
At a glance
- papers, 2023–2026
- 8/ year
- at T1 venues
- 73%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 15 papers2026 · T1 13 · collecting
- 9 papers2025 · T1 4
- 3 papers2024 · T1 2
- 3 papers2023 · T1 3
T1 venuesOtherVenues: DAC, ISCA, MICRO, HPCA, ASPLOS
Research focuspaper titles that use each topic's words
- Efficient training & inference10 papers
- Accelerators, chips & architecture3 papers
- training1 paper
- large-model training0 papers
- large-model0 papers
Paper list
From the lab homepage.
202615 papers
- ISCA (T1)Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs
- MICRO (T1)Beyond Linear Scaling for LLM Training on Wafer-Scale GPUs
- International Symposium on Advanced Parallel Processing Technolog（APPT ）BitFly: A Low-Bit Mixed-Precision Acceleration Framework for Edge RISC-V Vector Processors
- ICCAD (T1)DARA: A Data-Aware Refreshing Architecture for HBM Power Reduction in LLM Accelerators
- TCAS-IDRAM-Compatible Deterministic B2S Conversion Using Time-Weighted Comparison and DRAM-Resident Templates
- MICRO (T1)DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction
- HPCA (T1)FlashFuser: Expanding the Scale of Kernel Fusion for Compute-Intensive operators via Inter-Core Connection
- MICRO (T1)FlashGPU-sim: Enabling GPU Modeling for Modern Architectures and AI Workloads
- ASPLOS (T1)M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization
- ISCA (T1)MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
- ISCA (T1)Optimizing 3D Gaussian Splatting with Axis-Shared Rasterization and Order-independent Transmittance
- DAC (T1)PipeGS: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
20259 papers
- Proceedings of the International Symposium of EDA （ISEDA ）DATIS: DRAM Architecture and Technology Integrated Simulation
- Proceedings of the International Symposium of EDA （ISEDA ）DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators
- TCDSTC: Dual-Side Sparsity Tensor Core for DNNs Acceleration on Modern GPU Architectures
- T-CADFine-Grained Structured Sparse Computing for FPGA-Based AI Inference
- ISCA (T1)H^2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
- DAC (T1)MHDiff: Memory-and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization
- DAC (T1)SynGPU: Synergizing CUDA and Bit-Serial Tensor Cores for Vision Transformer Acceleration on GPU
- HPCA (T1)Tb-STC: Transposable Block-wise N:M Structured Sparse Tensor Core
- T-CADTheseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
20243 papers
- ASPLOS (T1)Amanda: Unified instrumentation framework for deep neural networks
- DAC (T1)Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation
- SCISTSCompiler: Efficient Compilation Framework for Dynamic-shape Models
20233 papers
- MICRO (T1)Cambricon-r: A fully fused accelerator for real-time learning of neural scene representation
- ISCA (T1)OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization
- MICRO (T1)RM-STC: Row-merge dataflow inspired GPU sparse tensor core for energy-efficient sparse acceleration
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
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