CNShanghai Jiao Tong UniversitySchool of Integrated Circuits (Information and Electronic Engineering)
Honglan Jiang
长聘教轨副教授
Works on energy-efficient neural network accelerators and approximate computing circuits.
Honglan Jiang's lab at SJTU works on accelerators, chips & architecture and efficient training & inference. 56 papers since 2023, 4 at top venues, mostly DAC and ISCA. Applications close .
At a glance
- papers, 2023–2026
- 15/ year
- at T1 venues
- 7%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage and DBLP, 2023–2026
- 21 papers2026 · T1 1 · collecting
- 15 papers2025 · T1 1
- 13 papers2024 · T1 1
- 7 papers2023 · T1 1
T1 venuesOtherVenues: DAC, ISCA
Research focuspaper titles that use each topic's words
- Efficient training & inference21 papers
- Accelerators, chips & architecture7 papers
- circuits3 papers
- network accelerators0 papers
- approximate computing0 papers
Paper list
From the lab homepage and DBLP.
202621 papers
- IEEE J. Solid State CircuitsA 1.8-to-3.0-GHz Fully Integrated All-in-One CMOS Frequency Management Module Achieving -47-/+42-ppm Inaccuracy From -40 ∘C to 95 ∘C and -150/+70 ppm After Accelerated Aging (opens in a new tab)
- ISCASA 10-Bit Successive Reference Approximation ADC Enabled By Switched-Capacitor Dynamic Reference Generation With Pipelined Pre-charging And Voltage Ripple Cancellation (opens in a new tab)
- IEEE J. Solid State CircuitsA 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From -40 °C to 85 °C and -560/+580 ppm After Accelerated Aging (opens in a new tab)
- IEEE J. Solid State CircuitsA Constant Bandwidth Oversampling PLL Enabled by a Constant-Gain Oversampler Composed of Double-Edge and Sampling Single-Edge Capacitive Charging and Discharging Phase Interpolators (opens in a new tab)
- Microelectron. J.A power-efficient multiplier with fine-grained power management (opens in a new tab)
- —Adana: Accelerating Large Language Models via Adaptive Nonuniform Asymmetric Quantization. Design Automation Conference (DAC), Long Beach, USA, 2026, pp. 1-7.
- —Adaptive Multiply-Accumulate Unit with Scalable Critical Path for Aggressive Voltage Underscaling DNN Accelerators. Design Automation Conference (DAC), San Francisco, USA, 2026, pp. 1-7.
- ISCASApproximate Signed Multiplier Designs for Efficient CNN Inference (opens in a new tab)
- IEEE J. Solid State CircuitsBASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of -247.9 dB at 3 GHz With a Ring Oscillator (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Beyond Uniform Approximation: Toward Efficient Computing in Logarithmic Number System for Large Language Models (opens in a new tab)
- —Beyond Uniform Approximation: Toward Efficient Computing in Logarithmic Number System for Large Language Models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026.
- DATEBridging the Power Estimation Gap: A GNN-Based Prediction Model for Approximate Logic Synthesis (opens in a new tab)
202515 papers
- ISSCC4.2 A 1.8-to-3.0GHz Fully Integrated All-In-One CMOS Frequency Management Module Achieving -47/+42ppm Inaccuracy from -40 to 95°C and -150/+70ppm After Accelerated Aging (opens in a new tab)
- DATEA Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks (opens in a new tab)
- —A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks. Design, Automation & Test in Europe (DATE), France, Lyon, 2025, pp. 1-7.
- IEEE Trans. Circuits Syst. I Regul. Pap.A Reference Oversampling PLL With a FoMREF of -240.1 dB Enabled By a Capacitive Parasitic-Proof Ring Oscillator and a Time-Multiplexed Gm Stage (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsEfficient Extraction and Packing Modules for Posit Multipliers (opens in a new tab)
- DAC (T1)EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit (opens in a new tab)
- —EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit. Design Automation Conference (DAC), San Francisco, USA, 2025, pp. 1-7.
- —J. Gross, Fabrizio Lombardi, and Jie Han, Approximate and Stochastic Ising Machines. IEEE Nanotechnology Magazine, 19(4): 44-53, 2025.
- DATELookup Table Refactoring: Towards Efficient Logarithmic Number System Addition for Large Language Models (opens in a new tab)
- —Lookup Table Refactoring: Towards Efficient Logarithmic Number System Addition for Large Language Models. Design, Automation & Test in Europe (DATE), France, Lyon, 2025, pp. 1-7.
- —Low-Power Multiplier Designs by Leveraging Correlations of 2×2 Encoded Partial Products. IEEE Transactions on Computers, 74 (11): 3888-3896, 2025.
- IEEE Trans. ComputersLow-Power Multiplier Designs by Leveraging Correlations of 2$\times$×2 Encoded Partial Products (opens in a new tab)
202413 papers
- DATEA Configurable Approximate Multiplier for CNNs Using Partial Product Speculation (opens in a new tab)
- —A Configurable Approximate Multiplier for CNNs using Partial Product Speculation. Design, Automation & Test in Europe (DATE), Valencia, Spain, 2024, pp. 1-6.
- ACM Great Lakes Symposium on VLSIA Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System (opens in a new tab)
- —A Low-Power and High-Accuracy Approximate Adder for the Logarithmic Number Systems, Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Clearwater, FL, USA, 2024, pp. 1-7.
- —Automated Generation and Evaluation of Application-Oriented Approximate Arithmetic Circuits, Chapter 14 in Weiqiang Liu, Jie Han, Fabrizio Lombardi (eds) Design and Applications of Emerging Computer Systems, Springer Nature, 2024, pp 353-377.
- —Cockburn, Leibo Liu, and Jie Han, Logarithmic Floating-Point Multipliers for Efficient Neural Network Training. Chapter 21 in Weiqiang Liu, Jie Han, Fabrizio Lombardi (eds) Design and Applications of Emerging Computer Systems, Springer Cham. 2024, pp 567-586.
- DATECompact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks (opens in a new tab)
- —Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks. Design, Automation & Test in Europe (DATE), Valencia, Spain, 2024, pp. 1-6.
- IEEE Trans. Circuits Syst. I Regul. Pap.Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications (opens in a new tab)
- IEEE Trans. ComputersLearning the Error Features of Approximate Multipliers for Neural Network Applications (opens in a new tab)
- —Learning the Error Features of Approximate Multipliers for Neural Network Applications. IEEE Transactions on Computers, 73(3), 842-856, 2024.
- DAC (T1)QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference (opens in a new tab)
20237 papers
- —A survey of majority logic designs in emerging nanotechnologies for computing. IEEE Transactions on Nanotechnology, Vol. 22, pp. 732-739, 2023.
- J. Comput. Sci. Technol.Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators (opens in a new tab)
- —Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators. Journal of Computer Science and Technology, 38(2): 309–327, 2023.
- —Cockburn, Leibo Liu, and Jie Han. Hardware-efficient logarithmic floating-point multipliers for error-tolerant applications. IEEE Transactions on Circuits and Systems I, 1-14, 2023.
- —COSA: Co-Operative Systolic Arrays for Multi-Head Attention Mechanism In Neural Network Using Hybrid Data Reuse And Fusion Methodologies. ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2023, pp. 1-6. (最佳论文提名)
- DAC (T1)COSA:Co-Operative Systolic Arrays for Multi-head Attention Mechanism in Neural Network using Hybrid Data Reuse and Fusion Methodologies (opens in a new tab)
- ISCASFeature-Embedding Triplet Networks with a Separately Constrained Loss Function (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
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- Self-funded
- Opens
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- GRE
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- English
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