CNShanghai Jiao Tong UniversitySchool of Integrated Circuits (Information and Electronic Engineering)
Yanan Sun
教授
Works on circuits and architectures for large-model inference acceleration and compute-in-memory 3D ICs.
Yanan Sun's lab at SJTU works on accelerators, chips & architecture and efficient training & inference. 12 papers since 2023, 3 at top venues, mostly DAC and ICCAD. Applications close .
At a glance
- papers, 2023–2026
- 3/ year
- at T1 venues
- 25%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 3 papers2026 · T1 0 · collecting
- 3 papers2025 · T1 1
- 2 papers2024 · T1 1
- 4 papers2023 · T1 1
T1 venuesOtherVenues: DAC, ICCAD
Research focuspaper titles that use each topic's words
- Efficient training & inference4 papers
- Accelerators, chips & architecture2 papers
- circuits0 papers
- large-model inference0 papers
- inference acceleration0 papers
Paper list
From the lab homepage.
20263 papers
- TCAS-IA Full-Digital Heterogeneous Computing-in-Memory with Dual-Bit Serialized Weight Stream and Ping-Pong Computing for Efficient Transformer Acceleration
- IEEE Transactions on Very Large Scale Integration (VLSI) SystemsA Heterogeneous CIM Architecture with Splittable Non-Volatile Computing-in-SRAM Cell-Pairs Enabling Efficient On-Chip Neural Network Inference
- TCADHEIRS-PS: Hybrid Three-dimensional RRAM- and SRAM-CIM for Pipelined Sparse Multi-Task Transformer Acceleration
20253 papers
- DAC (T1)HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsHyCTor: A Hybrid CNN-Transformer Network Accelerator with Flexible Weight/Output Stationary Dataflow and Multi-Core Extension
- TCAS-IRobust Monolithic 3D Carbon-Based Computing-in-SRAM with Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density
20242 papers
- IEEE Journal of Solid-State CircuitsA Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing with Single-Stage Synchronizer in Near-Threshold-Voltage Multi-Voltage/Frequency Domain Network-on-Chip
- DAC (T1)HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-Task Transformer Acceleration
20234 papers
- TCAS-IBC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory based on Memristive Crossbars
- TCAS-ICREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration
- ICTAHigh energy-efficient approximate in-SRAM computing with bit-wise compressor configuration and data-aware weight remapping method for neural network acceleration
- ICCAD (T1)TL-nvSRAM-CIM: Ultra-high-density three-level ReRAM-assisted computing-in-nvSRAM with DC-power free restore and ternary MAC operations
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
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Your notes
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Data
Some numbers could not be verified:
- The member list could not be found on the lab site.
- The alumni list could not be found on the lab site.
- Collected
- Verified
- Papers
- The lab homepage
- Members
- Not collected
- Alumni
- Not collected
Tiers are venue classifications, not lab rankings.
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