Priyanka Raina
Assistant Professor of Electrical Engineering
Designs energy-efficient hardware accelerators for machine learning and image processing.
Priyanka Raina's lab at Stanford works on accelerators, chips & architecture and efficient training & inference. 36 papers since 2023, 5 at top venues, mostly ASPLOS and DAC. 7 PhD students. 20 alumni. Applications close .
At a glance
- papers, 2023–2026
- 9/ year
- at T1 venues
- 14%
- PhD students
- 7
- MS students
- 0
- alumni listed
- 20
Papers by yearfrom the lab homepage, 2023–2026
- 7 papers2026 · T1 1 · collecting
- 9 papers2025 · T1 1
- 12 papers2024 · T1 1
- 8 papers2023 · T1 2
T1 venuesOtherVenues: ASPLOS, DAC, ICCAD, MICRO
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture8 papers
- Efficient training & inference5 papers
- energy-efficient hardware0 papers
- designs energy-efficient0 papers
- hardware accelerators0 papers
Paper list
From the lab homepage.
20267 papers
- Philosophical Transactions AA Methodology for Accurate Benchmarking of Neural Network Accelerators Using an HLS-Based Hardware Generator
- SSC-LBirch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator
- ASPLOS WorkshopPortable Dynamic Tiling for Sparse Tensor Accelerators
- YArchPortable Dynamic Tiling for Sparse Tensor Applications
- VLSIuAgent: A 7nm 404.3mJ/Action Edge SoC for Agentic AI Reasoning with Adaptive Block-wise Mixed-Format 4-bit Quantization and Decoupled Access-Execute
- DAC (T1)Voyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators
- ESSERCZircon: A 16nm Heterogeneous CGRA SoC for Accelerating Dense and Sparse ML
20259 papers
- CICCAspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads
- FMCADAutomated Translation Validation of a Compiler for Statically Scheduled Accelerators
- A-SSCCBirch: A Real-Time Accelerator for Multi-Task Mixed-Domain Extended Reality Perception Workloads
- MICRO (T1)Designing Programmable Accelerators for Sparse Tensor Algebra
- JSSCMINOTAUR: A Posit-Based 0.42-0.50 TOPS/W Edge Transformer Inference and Training Accelerator
- T-EDMonolithic 3D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS
- JSSCOnyx: A 12nm Programmable Accelerator for Dense and Sparse Applications
- CICCOpal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications
- SSC-LOpal: A 16nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications
202412 papers
- ASPLOS (T1)8-bit Transformer Inference and Fine-tuning for Edge Accelerators
- ISCA WorkshopA High-Level Synthesis Based Framework for Design Space Exploration and Generation of Neural Network Accelerators
- ISCA WorkshopAHA: An Open-Source Framework for Co-design of Programmable Accelerators and Compilers
- TCADCascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
- IEDMEdge Continual Training and Inference with RRAM-Gain Cell Memory Integrated on Si CMOS
- FMCADEfficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection
- JSSCEMBER: Efficient Multiple-Bits-per-Cell Embedded RRAM Macro for High-Density Digital Storage
- ISQEDFastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization
- VLSIMINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating
- VLSIOnyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications
- IEEE Hot Chips SymposiumOnyx: A Programmable Accelerator for Sparse Tensor Algebra
- TECSPEak: A Single Source of Truth for Hardware Design and Verification
20238 papers
- Integration3-D Coarse-Grained Reconfigurable Array Using Multi-Pole NEM Relays for Programmable Routing
- JSSCAmber: A 16nm System-on-Chip with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
- ISCASAn Open-Source 4x8 Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow
- ASPLOS (T1)APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
- CALCanal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
- ESSCIRCEMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry
- ICCAD (T1)PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM
- DATEUltra-Dense 3D Physical Design Enables New Architectural Design Points with Large Benefits
Where alumni went20 listed, 0% to industry
Industry 0Academia 1
Also to
- Purdue University in 2023
Apply to StanfordFall 2027
Stanford Computer Science PhD
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