Ningyi Xu
Tenured Professor
Works on hardware acceleration and computing systems for AI in the Qing Yuan Research Institute.
Ningyi Xu's lab at SJTU works on accelerators, chips & architecture. 39 papers since 2023, 16 at top venues, mostly DAC and ICCAD. Applications close .
At a glance
- papers, 2023–2026
- 10/ year
- at T1 venues
- 41%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 4 papers2026 · T1 1 · collecting
- 13 papers2025 · T1 6
- 13 papers2024 · T1 4
- 9 papers2023 · T1 5
T1 venuesOtherVenues: DAC, ICCAD, ECCV, AAAI, ACL
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture9 papers
- hardware4 papers
- acceleration1 paper
- hardware acceleration0 papers
- computing systems0 papers
Paper list
From DBLP.
20264 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.MARCA-v2: Mamba Accelerator With Complementary State-Space Model Sparsity and Reconfigurable Architecture (opens in a new tab)
- AAAI (T1)MoSs: Mixture of Scales for Efficient High-Resolution Autoregressive Image Generation (opens in a new tab)
- DATERAMP: RTL-Level Emulation with Thousand-Core-Scale Parallelism (opens in a new tab)
- ASP-DACROMA: A Read-Only-Memory-based Accelerator for QLoRA-based On-Device LLM (opens in a new tab)
202513 papers
- DAC (T1)A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Point Transformer Accelerator With Distribution-Aware Heuristic Distance Calculation (opens in a new tab)
- ICLR (T1)DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale (opens in a new tab)
- DATEDyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Partitioning, Low-Degree Sparsity, and Asynchronous Sub-Batch (opens in a new tab)
- IEEE J. Emerg. Sel. Topics Circuits Syst.Efficient Hardware Architecture Design for Rotary Position Embedding of Large Language Models (opens in a new tab)
- Adv. Eng. Softw.Efficient multi-GPU implementations of preconditioned conjugate gradient method (opens in a new tab)
- NeurIPS (T1)Hierachical Balance Packing: Towards Efficient Supervised Fine-tuning for Long-Context LLM (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems (opens in a new tab)
- ASP-DACLLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration (opens in a new tab)
- ECAILoRA Decompose: Serving Fine-Tuned Models into LoRA-Like (opens in a new tab)
- ICML (T1)OmniBal: Towards Fast Instruction-Tuning for Vision-Language Models via Omniverse Computation Balance (opens in a new tab)
- ICRA (T1)SARO: Space-Aware Robot System for Terrain Crossing via Vision-Language Model (opens in a new tab)
202413 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Precision-Scalable Deep Neural Network Accelerator With Activation Sparsity Exploitation (opens in a new tab)
- Findings of ACLAFPQ: Asymmetric Floating Point Quantization for LLMs (opens in a new tab)
- ACL (T1)BitDistiller: Unleashing the Potential of Sub-4-Bit LLMs via Self-Distillation (opens in a new tab)
- IEEE Trans. ComputersCoDA: A Co-Design Framework for Versatile and Efficient Attention Accelerators (opens in a new tab)
- ECCV (T1)Enhancing Vectorized Map Perception with Historical Rasterized Maps (opens in a new tab)
- Sci. China Inf. Sci.Hardware-oriented algorithms for softmax and layer normalization of large language models (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators (opens in a new tab)
- ICMEInteger or Floating Point? New Outlooks for Low-Bit Quantization on Large Language Models (opens in a new tab)
- ECCV (T1)Leveraging Enhanced Queries of Point Sets for Vectorized Map Construction (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture (opens in a new tab)
- ICCAD (T1)MARCA: Mamba Accelerator with Reconfigurable Architecture (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.Quantization and Hardware Architecture Co-Design for Matrix-Vector Multiplications of Large Language Models (opens in a new tab)
20239 papers
- ICCAD (T1)A Point Transformer Accelerator with Fine-Grained Pipelines and Distribution-Aware Dynamic FPS (opens in a new tab)
- ECAIAdam Accumulation to Reduce Memory Footprints of Both Activations and Gradients for Large-Scale DNN Training (opens in a new tab)
- DAC (T1)COSA:Co-Operative Systolic Arrays for Multi-head Attention Mechanism in Neural Network using Hybrid Data Reuse and Fusion Methodologies (opens in a new tab)
- MLSys (T1)Exploiting Hardware Utilization and Adaptive Dataflow for Efficient Sparse Convolution in 3D Point Clouds (opens in a new tab)
- DAC (T1)FLNA: An Energy-Efficient Point Cloud Feature Learning Accelerator with Dataflow Decoupling (opens in a new tab)
- MMAsiaHistory-Detr: Optimize Query Initialization Strategy by Using Historical Information and Kinematics (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsLow-Complexity Precision-Scalable Multiply-Accumulate Unit Architectures for Deep Neural Network Accelerators (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsNVP: A Flexible and Efficient Processor Architecture for Accelerating Diverse Computer Vision Tasks including DNN (opens in a new tab)
- ICCAD (T1)SpOctA: A 3D Sparse Convolution Accelerator with Octree-Encoding-Based Map Search and Inherent Sparsity-Aware Processing (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
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- Fee
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Not yet confirmed for this intake.
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