Xueqing Li
Associate Professor
Works on circuits and architectures with emerging devices, including compute-in-memory for AI.
Xueqing Li's lab at Tsinghua works on accelerators, chips & architecture. 43 papers since 2023, 12 at top venues, mostly DAC and ICCAD. Applications close .
At a glance
- papers, 2023–2026
- 11/ year
- at T1 venues
- 28%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 2 papers2026 · T1 0 · collecting
- 16 papers2025 · T1 3
- 12 papers2024 · T1 5
- 13 papers2023 · T1 4
T1 venuesOtherVenues: DAC, ICCAD, CCS
Research focuspaper titles that use each topic's words
- compute-in-memory13 papers
- Accelerators, chips & architecture11 papers
- emerging1 paper
- devices1 paper
- emerging devices0 papers
Paper list
From the lab homepage.
20262 papers
- Design, Automation & Test in Europe Conference & Exhibition (DATE)EGO: Efficient Compression of Unstructured Sparse DNNs for Compute-in-Memory based on Graph Minimum-Cost Matching Optimization
- Design, Automation & Test in Europe Conference & Exhibition (DATE)FSDB: A Folded-Store Dynamic-Broaden Hybrid Compute-in-ROM/SRAM Architecture for Deploying Large-Scale DNNs On-Chip
202516 papers
- CICC18-3: Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI tasks
- ISCAS3D-Domino: Ultra-Dense High-Accuracy 3D eDRAM-ROM Compute-in-Memory Based on CAA-IGZO TFT for Edge Large-Scale Model Inference
- ASP-DAC3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro
- CCMCCA 28nm 26.9 Mb/mm² x 43.1 TOPS/W Fully Digital Task-Flexible Compute-in-ROM/SRAM Macro for Energy-Efficient Edge AI Inference
- ASSCCA 28nm 68.6TOPS/W Folded-Differential Switched-Capacitor FIA-Based SRAM CIM Macro with Scalable Mac Sizes for Tiny-ML Inference
- ESSERCA 28nm 8-Bit 32-GS/S DAC Achieving > 55dBc/> 40dBc SFDR Up to 5.2GHz/13.6GHz Using 4-Channel NRZ Time-Interleaving with Background Calibration for Direct Digital Signal Synthesis
- GLSVLSIADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory
- ICCAD (T1)DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AI
- ASP-DACDCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level
- DAC (T1)DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture
- DATEDSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for On-Chip Deployment of Large-Scale DNNs
- ESSERCEnabling Energy-Efficient and High-Density eDRAM-LUT-Based Computing-in-Memory Using Anti-Ferroelectric Transistors
202412 papers
- ISCASA 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity
- CICCA 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS
- CICCA 28nm 8928Kb/mm2-weight-density hybrid SRAM/ROM Compute-in-Memory architecture reducing >95% weight loading from DRAM
- DATECafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging
- CCS (T1)CiMSAT: Exploiting SAT Analysis to Attack Compute-in-Memory Architecture Defenses
- DAC (T1)Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory
- IEDMFirst Demonstration of AFeFET-Based Capacitor-Less eDRAM Computing-in-Memory Featuring 4.84 Mb/mm^2 High Memory Density, 10^5 s Long Retention Time, and >10^10 High Endurance
- DAC (T1)HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration
- ICCAD (T1)NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data
- ICCAD (T1)REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control
- DATETroScan: Enhancing On-Chip Delivery Resilience to Physical Attack through Frequency-Triggered Key Generation
- ASP-DACZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns
202313 papers
- IEDM30 Mb/mm2/layer 3D eDRAM Computing-in-Memory with Embedded BEOL Peripherals and Local Layer-wise Calibration based on First-Demonstrated Vertically- stacked CAA-IGZO 4F2 2T0C Cell
- ISSCCA 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse Digital Architecture
- ISSCCA 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference
- IEEE Symposium on VLSI Technology and CircuitsA 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro
- IFETCA 66.67kHz 4.953 nJ/Conv-Step 5b Fully Integrated Asynchronous SAR ADC Using 4μm LTPS TFTs
- ASSCCA 7nm 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging Technology
- DAC (T1)ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory
- ISVLSIDesign Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays
- ISVLSIFe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks
- ICCAD (T1)Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices
- ICCAD (T1)TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations
- DAC (T1)Victor: A Variation-resilient Approach Using Cell-clustered Charge-domain computing for High-density High-throughput MLC CiM
Where alumni went
Alumni are not listed on the lab homepage.
Apply to TsinghuaFall 2027
Computer Science PhD (international applicants)
- Round
- Main
- Opens
- GRE
- See program page
- English
- Per school catalog
- Fee
- RMB 800
Not yet confirmed for this intake.
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