Yongpan Liu
Professor
Works on AI chips, sensing-storage-computing integrated chips and systems, and emerging memories.
Yongpan Liu's lab at Tsinghua works on accelerators, chips & architecture and distributed, cloud & edge systems. 98 papers since 2023, 10 at top venues, mostly ICCAD and DAC. Applications close .
At a glance
- papers, 2023–2026
- 26/ year
- at T1 venues
- 10%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 20 papers2026 · T1 2 · collecting
- 25 papers2025 · T1 3
- 24 papers2024 · T1 0
- 29 papers2023 · T1 5
T1 venuesOtherVenues: ICCAD, DAC, ISCA, AAAI, MLSys
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture21 papers
- Distributed, cloud & edge systems13 papers
- chips1 paper
- emerging1 paper
- integrated0 papers
Paper list
From DBLP.
202620 papers
- ISSCC2.10 A 1286fps 0.39mJ/Frame Modeling/Rendering Unified 3D GS Processor with Locality-Optimized Computation and Reconfigurable Architecture (opens in a new tab)
- IEEE J. Solid State CircuitsA 28-nm Computing-in-Memory Processor With Zig-Zag Backbone-Systolic CIM and Block-/Self-Gating CAM for NN/Recommendation Applications (opens in a new tab)
- IEEE J. Solid State CircuitsA 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.A 28-nm Versatile TinyML SoC With Flexible Hetero-Fabric Dataflow Orchestration and Compute/Storage-Density-Adjustable CIM (opens in a new tab)
- IEEE J. Solid State CircuitsA Compact Energy-Efficient Unified Micro-Robotic Processor With Flexible Visual Perception (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA High-SNR SRAM-LUT-Based In-Memory-Computing Macro Supporting Energy-Efficient INT8 and FP8 Computation (opens in a new tab)
- IEEE Wirel. Commun. Lett.A Novel Constraint-Aware Scheduling Algorithm for Computing and Communication Satellite Constellation Resources (opens in a new tab)
- DATEA Real-Time Robotic Diffusion Policy Accelerator Exploiting Self- and Cross-Guided Modal Similarity (opens in a new tab)
- IEEE J. Solid State CircuitsAn Area-Efficient Lookup-Table -Based eDRAM Digital CIM Macro for Neural Network Inference (opens in a new tab)
- IEEE J. Solid State CircuitsAn Edge 3-D Gaussian Splatting Processor Based on Shape-Aware Computation Architecture and Spatio-Temporal Gaussian Cache (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.ApproPower: Characterizing the Power Side-Channel Features of Approximate Multipliers With Symbolic Path Analysis (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.BVDT: A 28-nm LUT-Assisted Transformer Accelerator With Basis-Vector Compression and Decomposed Computing (opens in a new tab)
202525 papers
- ISSCC1.78mJ/Frame 373fps 3D GS Processor Based on Shape-Aware Hybrid Architecture Using Earlier Computation Skipping and Gaussian Cache Scheduler (opens in a new tab)
- ASP-DAC3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro (opens in a new tab)
- CCMCCA 28nm 26.9 Mb/mm2 x 43.1 TOPS/W Fully Digital Task-Flexible Compute-in-ROM/SRAM Macro for Energy-Efficient Edge AI Inference (opens in a new tab)
- CICCA 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC (opens in a new tab)
- IEEE J. Solid State CircuitsA Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference (opens in a new tab)
- IEEE J. Solid State CircuitsA Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit (opens in a new tab)
- ISCASA Threshold-Voltage Compensation Circuit for Organic Thin-Film Transistor Active-Matrix Neurostimulation System (opens in a new tab)
- ACM Great Lakes Symposium on VLSIADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory (opens in a new tab)
- ISCASAn Integer-only Quantization Framework for Edge Deployment of Large Language Models (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet (opens in a new tab)
- CICCCCE: A 28nm Content Creation Engine with Asymmetric Computing, Semantic-Driven Instruction Generation and Collision-Free Outlier Mapper for Video Generation (opens in a new tab)
- ICCAD (T1)DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AI (opens in a new tab)
202424 papers
- ISSCC34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing (opens in a new tab)
- ISCASA 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity (opens in a new tab)
- IEEE J. Solid State CircuitsA 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching (opens in a new tab)
- IEEE J. Solid State CircuitsA 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture (opens in a new tab)
- CICCA 28nm 1.2GHz 5.27TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion Applications (opens in a new tab)
- A-SSCCA 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices (opens in a new tab)
- VLSI Technology and CircuitsA 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-Assisted Cores (opens in a new tab)
- CICCA 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM (opens in a new tab)
- VLSI Technology and CircuitsA 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications (opens in a new tab)
- IEEE J. Solid State CircuitsA Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA Fully Quantized Training Accelerator for Diffusion Network With Tensor Type & Noise Strength Aware Precision Scheduling (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA Heterogeneous Microprocessor for Intermittent AI Inference Using Nonvolatile-SRAM-Based Compute-In-Memory (opens in a new tab)
202329 papers
- CICCA 28nm 1.07TFLOPS/mm2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing (opens in a new tab)
- ISSCCA 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture (opens in a new tab)
- ISSCCA 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network (opens in a new tab)
- ISSCCA 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference (opens in a new tab)
- A-SSCCA 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation (opens in a new tab)
- VLSI Technology and CircuitsA 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro (opens in a new tab)
- AICASA Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference (opens in a new tab)
- ISCASA User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsA Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution (opens in a new tab)
- IEEE J. Solid State CircuitsAn In-Memory-Computing Charge-Domain Ternary CNN Classifier (opens in a new tab)
- IEEE Trans. Circuits Syst. II Express BriefsAn RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to TsinghuaFall 2027
Computer Science PhD (international applicants)
- Round
- Main
- Opens
- GRE
- See program page
- English
- Per school catalog
- Fee
- RMB 800
Not yet confirmed for this intake.
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