Christopher Torng
Assistant Professor of Electrical and Computer Engineering and Computer Science
Builds domain-specific hardware accelerators and agile chip design flows in the ACORN group.
Christopher Torng's lab at USC works on accelerators, chips & architecture. 14 papers since 2023. 7 PhD students and 1 master's student. 13 alumni, most often to NVIDIA and Apple. Applications close .
At a glance
- papers, 2023–2026
- 4/ year
- at T1 venues
- 0%
- PhD students
- 7
- MS students
- 1
- alumni listed
- 13
Papers by yearfrom the lab homepage, 2023–2026
- 3 papers2026 · T1 0 · collecting
- 1 papers2025 · T1 0
- 5 papers2024 · T1 0
- 5 papers2023 · T1 0
T1 venuesOther
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture3 papers
- agile1 paper
- flows0 papers
- hardware accelerators0 papers
- chip design0 papers
Paper list
From the lab homepage.
20263 papers
- To Appear at IEEE/ACM International Symposium on Microarchitecture (MICRO), OctoberCapstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers
- To Appear at IEEE/ACM International Conference on Computer-Aided Design (ICCAD), NovemberChipstitch: A Scalable and Cost-Efficient Platform for Accelerated Silicon Prototyping
- IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), AugustPowerFlow-DNN: Compiler-Directed Fine-Grained Power Orchestration for End-to-End Edge AI Inference
20251 paper
- IEEE Journal of Solid-State Circuits (JSSC), SeptemberOnyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications
20245 papers
- European Solid-State Electronics Research Conference (ESSERC), SeptemberA 3.25GHz Large-Integer Extended GCD Accelerator in 12nm
- Workshop on Open-Source Computer Architecture Research (OSCAR) co-located with ISCA, JuneAHA: An Open-Source Framework for Co-design of Programmable Accelerators and Compilers
- IEEE Journal of Solid-State Circuits (JSSC), MarchAmber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
- IEEE Symposium on VLSI Technology and Circuits (VLSI), JuneOnyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications
- Symposium on High Performance Chips (Hot Chips), AugustOnyx: A Programmable Accelerator for Sparse Tensor Algebra
20235 papers
- Workshop on Open-Source Computer Architecture Research (OSCAR) co-located with ISCA, JuneA Fast Open-Source Extended GCD Accelerator
- ACM Transactions on Embedded Computing Systems (TECS), JanuaryAHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
- Workshop on Computer Architecture Education (WCAE) co-located with ISCA, JuneBuilding First-Order Energy Modeling Intuition in Computer Architecture Lectures
- IEEE Computer Architecture Letters (CAL), AprilCanal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
- ACM Transactions on Reconfigurable Technology and Systems (TRETS), AprilImproving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
Where alumni went13 listed, 86% to industry
Industry 6Academia 1
Most often to
- NVIDIA
- Apple
- Annapurna Labs
Also to
- USC
Apply to USCFall 2027
Computer Science PhD (Viterbi)
- Round
- Single round (Dec 15)
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Confirmed on the program page.
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- The lab homepage
- Members
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