C. J. Richard Shi
Professor
Designs machine learning hardware, integrated circuits and electronic design automation tools.
C. J. Richard Shi's lab at UW works on accelerators, chips & architecture. 28 papers since 2023. 2 PhD students and 2 master's students. 39 alumni. Applications close .
At a glance
- papers, 2023–2026
- 7/ year
- at T1 venues
- 0%
- PhD students
- 2
- MS students
- 2
- alumni listed
- 39
Papers by yearfrom DBLP, 2023–2026
- 8 papers2026 · T1 0 · collecting
- 12 papers2025 · T1 0
- 3 papers2024 · T1 0
- 5 papers2023 · T1 0
T1 venuesOther
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture2 papers
- hardware1 paper
- electronic design0 papers
- design automation0 papers
- tools0 papers
Paper list
From DBLP.
20268 papers
- ISSCCA 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling (opens in a new tab)
- CICCA 256-Channel, 3.49-mW Wireless Neural Recording SoC with Adaptive Delta Compression and Error-Resilient Coding (opens in a new tab)
- ISCASA 28nm 56.45TOPS/W Hardware-software Co-optimized Sparse Accelerator for Traditional DNNs and Transformer-based LLMs (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.A 39.4-μW 915-MHz Third-Harmonic Mixing Receiver With On-Chip LO Achieving -86-dBm Sensitivity and Multichannel Selection (opens in a new tab)
- ISCASAn All-MOS 1-nA Current Reference Insensitive to Process and Voltage Variations (opens in a new tab)
- ISCASAn Injection-Locked Eight Phase Clock Generator with Edge Replacement and Injection Error Calibration Achieving -253.7dB FOMJitter-N (opens in a new tab)
- ISCASAn Optimized Pre-Emphasis Spike Detector for High-Density Neural Interfaces (opens in a new tab)
- FCCMTransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines (opens in a new tab)
202512 papers
- ISCASA 0.473 μJ/class Seizure Detection Processor with LSVM Classifier and LPF-Based Feature Extraction (opens in a new tab)
- IEEE J. Solid State CircuitsA 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity (opens in a new tab)
- ISCASA 240-mV 33.8-μV/°C 1.5-nW Voltage Detector for Energy Harvesting (opens in a new tab)
- ISCASA 40µW 915MHz Receiver with Sub-Passive Third-Harmonic Mixer Achieving -88dBm Sensitivity and Multi-Channel Selection (opens in a new tab)
- ISCASA 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity (opens in a new tab)
- ISCASA Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N (opens in a new tab)
- ACM Trans. Embed. Comput. Syst.A Workload-Balance-Aware Accelerator Enabling Dense-to-Arbitrary-Sparse Neural Networks (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving -251.9 dB FOMJitter-N (opens in a new tab)
- ACM Great Lakes Symposium on VLSIHCSAs: Hybrid Computing Systolic Arrays for Accelerating Mamba Models with Unified State Space Buffers and Energy-Efficient Dataflow (opens in a new tab)
- ACM Great Lakes Symposium on VLSILEGO: A 12nm FinFET Analog Cell Library for Analog/Mixed-Signal Applications (opens in a new tab)
- ASAPReaLLM: A Trace-Driven Framework for Rapid Simulation of Large-Scale LLM Inference (opens in a new tab)
- SymmetryTimed-Elastic-Band-Based Variable Splitting for Autonomous Trajectory Planning (opens in a new tab)
20243 papers
- CICCA -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR (opens in a new tab)
- SensorsFall Detection System Based on Point Cloud Enhancement Model for 24 GHz FMCW Radar (opens in a new tab)
- IEEE Trans. Neural Networks Learn. Syst.SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification (opens in a new tab)
20235 papers
- A-SSCCA 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction (opens in a new tab)
- ESSCIRCA 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF (opens in a new tab)
- IEEE Trans. Parallel Distributed Syst.Accelerating Distributed GNN Training by Codes (opens in a new tab)
- J. Supercomput.Augmenting aspect-level sentiment classification with distance-related local context input (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices (opens in a new tab)
Where alumni went39 listed
Apply to UWFall 2027
UW Allen School Computer Science PhD
- Round
- Single round
- Opens
- GRE
- not required
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
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