Tae Hyoung Kim
Associate Professor
Designs computing-in-memory circuits for machine learning and robust low-power memory and subthreshold circuits.
Tae Hyoung Kim's lab at NTU works on accelerators, chips & architecture. 74 papers since 2023, 1 at top venues, mostly MICRO. 5 PhD students and 14 master's students. 24 alumni.
At a glance
- papers, 2023–2026
- 19/ year
- at T1 venues
- 1%
- PhD students
- 5
- MS students
- 14
- alumni listed
- 24
Papers by yearfrom the lab homepage, 2023–2026
- 18 papers2026 · T1 1 · collecting
- 12 papers2025 · T1 0
- 25 papers2024 · T1 0
- 19 papers2023 · T1 0
T1 venuesOtherVenues: MICRO
Research focuspaper titles that use each topic's words
- memory24 papers
- Accelerators, chips & architecture3 papers
- robust1 paper
- circuits0 papers
- low-power0 papers
Paper list
From the lab homepage.
202618 papers
- IEEE International Symposium on Circuits and SystemsA 0.74 pJ/Bit 10 Gbps PAM-4 Transceiver with Triple TIA Termination and Power-Saving Addition-Only Driving for Parallel Memory Interface Channels
- IEEE Transactions on VLSI Systems, doi: 10.1109/TVLSI. .3676995A 65-nm 3T2R ReRAM Computing-in-Memory Macro Using a 4-bit 1 GS/s Two-stage Pipelined 2-bit Output Comparator with a Successive Approximation-like Architecture
- IEEE Journal of Solid-State CircuitsA BEV Perception Transformer Accelerator with Saliency-Driven Image/Point Cloud Fusion and Phase-Linked Dataflow in 28nm CMOS
- IEEE Transactions on Circuits and Systems-IA Compact Dual-Mode SAR ADC With Mismatch Error Shaping Using Prediction-Error-Free 3-Level Analog Prediction and 1-Bit Barrel-Shift Dithering
- IEEE International Conference on Artificial Intelligence Circuits and SystemsA Hardware-Oriented Event-Driven Gesture Recognition System with a Geometry-Token Early-Exit Classifier for a Perovskite Vision Platform
- International SoC Design ConferenceA PAM-4 Receiver with Time-Domain 2-Tap FIR and 1-Tap IIR DFE
- IEEE Transactions on VLSI SystemsA Real-Time End-to-End Event-based Tactile Sensing System
- Circuits, Systems, and Signal ProcessingA Time-based PAM-4 Transceiver using Linear Voltage-to-Time Converter and Single Path PAM-4 Decoder with Fast-Stochastic Calibration
- Microelectronics JournalA Yield-Resilient 1Mb RRAM Macro with Bipolar Forming and Cell-by-Cell Write Verification
- IEEE European Solid-State Electronics Research ConferenceAn AR/VR SoC with Dual-Mode Gaze Guided Perception and Few-Shot Keyword Spotting
- IEEE Journal of Solid-State CircuitsAn Ultra-Low Energy Environmental Sound Recognition Processor with Adaptive Learning for Intelligent Edge Devices
- MICRO (T1)Despoina: Depth-Amortized Incremental Inference for Deep Dynamic GNN Acceleration
202512 papers
- IEEE Asia Pacific Conference on Circuits and Systems3ETSS: An Energy-Efficient Event-based Tactile Sensing System
- IEEE International Symposium on Circuits and SystemsA 1Mb RRAM Macro with Bipolar Foaming for Improved Programming Yield and Cell-by-cell Write Verification Scheme
- IEEE Transactions on Circuits and Systems-IA 2.793µW Near-Threshold Neuronal Population Dynamics Trajectory Filter for Reliable Simultaneous Localization and Mapping
- The International Technical Conference on Circuits/Systems, Computers, and CommunicationsA 20-Gb/s Half-Rate PAM-4 Receiver With Time-Based FIR-IIR DFE
- IEEE Transactions on VLSI SystemsA 65nm 55.8TOPS/W Compact 2T DRAM-Based Compute-in-Memory Accelerator with Linear Calibration
- IEEE Asian Solid-State Circuits ConferenceA 96pJ/Frame/Pixel and 61pJ/Event anti-UAV System with Hybrid Object Tracking Modes
- IEEE Transactions on Circuits and Systems-IA Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Enhancements
- IEEE Custom Integrated Circuits ConferenceA High Accuracy and Ultra-Low Energy Environmental Sound Recognition Processor with Progressive Spectrogram Processing and Adaptive Weight Clustering based Online Learning
- IET Electronics LettersBackground Injection-Pulse Duty Correction with 0.05% Accuracy for Dual-Edge ILPLL using Sub-Sampling Charge Pump
- IEEE Solid-State Circuits LettersConvolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving
- IEEE Transactions on Circuits and Systems-IFlexDCIM: A 400MHz 249.1TOPS/W 64Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration
- IEEE Journal of Solid-State CircuitsSESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices
202425 papers
- IEEE Custom Integrated Circuits ConferenceA 0.0042nJPixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-path Aggregation Semi-Global Matching
- IEEE Transactions on Circuits and Systems-IA 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣADC Suitable for DVFS
- IEEE International Symposium on Circuits and SystemsA 1-Mb RRAM Macro with 9.8ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation
- IEEE Asian Solid-State Circuits ConferenceA 1.12nJ/Pixel High-Accuracy and Memory-Efficient Real-Time Event-Driven Object Detection Processor for Dynamic Neuromorphic Vision Sensors
- IEEE Asian Solid-State Circuits ConferenceA 10.5 Gbps 0.55 pJ/bit PAM-3 Transceiver Using a Self-driven Dual TIA Receiver and Floating Impedance Matching for Parallel On-chip Transmission Lines
- IEEE Journal of Solid-State CircuitsA 2.5 GHz Dynamic Performance-Enhanced Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process
- IEEE International Symposium on Circuits and SystemsA 2.793µW Near-Threshold Neuronal Population Dynamics Simulator for Reliable Simultaneous Localization and Mapping
- IEEE Asian Solid-State Circuits ConferenceA 280.580 μm2 /Grid, 30.7pJ/12.5MHz TMRA-PIM (Time-Multiplexed Random-Access Processing-in-Memory) Accelerator for Partial Differential Equations with Programmable Boundary Conditions
- IEEE Transactions on Circuits and Systems-IA Dual 7T SRAM-Based Zero-Skipping Computing-In-Memory Macro with 1-6b Binary Searching ADCs for Processing Quantized Neural Networks
- The Intl. Conf. on Electronics, Information, and CommunicationA Dynamic Gesture Recognition Algorithm Using Single Halide Perovskite Photovoltaic Cell for Human-Machine Interaction
- SensorsA High-Resolution Discrete-Time 2nd-order ΣΔ ADC with Improved Tolerance to KT/C Noise using Low Oversampling Ratio
- IEEE International Symposium on Circuits and SystemsA Memory-Efficient High-Speed Event-Based Object Tracking System
202319 papers
- IEEE International Symposium on Circuits and Systems282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing
- IEEE Transactions on Circuits and Systems-IA 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks
- IEEE Journal of Solid-State CircuitsA 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN
- IEEE Asian Solid-State Circuits ConferenceA 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Basd Digital Compute-In-Memory Macro for Accelerating CNNs
- IEEE Solid-State Circuits LettersA 6 Gbps PAM-3 Transceiver with Background Time-Varying Offset Sensing and Compensation
- IEEE Symposium on VLSI CircuitsA Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations
- IEEE Custom Integrated Circuits ConferenceA Continuous-Time Ising Machine Using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates
- IEEE International Symposium on Circuits and SystemsA Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration
- IEEE International Symposium on Circuits and SystemsA Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing
- IEEE Solid-State Circuits LettersA Reconfigurable CMOS Ising Machine with Three-Body Spin Interactions for Solving Boolean Satisfiability with Direct Mapping
- IEEE Custom Integrated Circuits ConferenceA Reconfigurable Ising Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions
- IEEE Transactions on Circuits and Systems-IA Robust Time-based Multi-level Sensing Circuit for Resistive Memory
Where alumni went24 listed
Apply to NTUFall 2027
Not announced yet
Computing and Data Science PhD
- Round
- Main
- Opens
- —
- GRE
- not required
- English
- TOEFL/IELTS
- Fee
- See program page
Not yet confirmed for this intake.
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