CNShanghai Jiao Tong UniversitySchool of Integrated Circuits (Information and Electronic Engineering)
Jianfei Jiang
副研究员
Works on 2.5D/3D integrated chips, SoC architecture and neural network acceleration circuits.
Jianfei Jiang's lab at SJTU works on accelerators, chips & architecture. 11 papers since 2023, mostly Expert Systems with Applications. Applications close .
At a glance
- papers, 2023–2026
- 3/ year
- at T1 venues
- 0%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 2 papers2026 · T1 0 · collecting
- 3 papers2025 · T1 0
- 2 papers2024 · T1 0
- 4 papers2023 · T1 0
T1 venuesOtherVenues: Expert Systems with Applications
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture2 papers
- acceleration1 paper
- neural network1 paper
- integrated0 papers
- circuits0 papers
Paper list
From the lab homepage.
20262 papers
- IEEE Custom Integrated Circuits Conference (CICC)A 51.19 mm2, 4 TB/s bandwidth 3D Logic-on-SRAM Stacking CGRA Chip
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDIONet3D: Dual-Input Dual-Output Deep Neural Network with 3D-Enhanced PDN Feature for IR Drop Prediction in 3D ICs
20253 papers
- IEEE Transactions on Very Large Scale Integration (VLSI) SystemsA Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip
- IEEE Transactions on Circuits and Systems II: Express BriefsAn Energy Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2
- IEEE Journal on Emerging and Selected Topics in Circuits and SystemsEfficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System
20242 papers
- IEEE International Symposium on Circuits and Systems (ISCAS)A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction
- Expert Systems with ApplicationsA Novel Vehicle Collision Detection System: Integrating Audio-Visual Fusion for Enhanced Performance
20234 papers
- IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)A Hierarchical Communication Algorithm for Distributed Deep Learning Training
- IEEE Electronic Components and Technology Conference (ECTC)A Method to Improve 3D Interconnections Resource Utilization and Reliability in Hybrid Bonding Process Considering the Effects on Signal Integrity
- Integration, the VLSI JournalExploiting Bit Sparsity in Both Activation and Weight in Neural Networks Accelerators
- IEEE International Conference on ASIC (ASICON)MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
Similar labsnearest by research summary
- SGNTU
Suhas Kumar
- Accelerators, chips & architecture
- USUW
C. J. Richard Shi
- Accelerators, chips & architecture
- CHETH Zurich
Melika Payvand
- Accelerators, chips & architecture
- SGNTU
Tae Hyoung Kim
- Accelerators, chips & architecture
- CNTsinghua
Hongwei Chen
- Accelerators, chips & architecture
- CNZhejiang
Xunzhao Yin
- Accelerators, chips & architecture
Your notes
Save this lab to keep notes.
Data
Some numbers could not be verified:
- The member list could not be found on the lab site.
- The alumni list could not be found on the lab site.
- Collected
- Verified
- Papers
- The lab homepage
- Members
- Not collected
- Alumni
- Not collected
Tiers are venue classifications, not lab rankings.
SJTUcloses