Tushar Krishna
Assistant Professor
Designs hardware accelerators and interconnection networks for machine learning.
Tushar Krishna's lab at Georgia Tech works on accelerators, chips & architecture. 87 papers since 2023, 43 at top venues, mostly MLSys and HPCA. Applications close .
At a glance
- papers, 2023–2026
- 23/ year
- at T1 venues
- 49%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 27 papers2026 · T1 16 · collecting
- 25 papers2025 · T1 14
- 16 papers2024 · T1 6
- 19 papers2023 · T1 7
T1 venuesOtherVenues: MLSys, HPCA, MICRO, ASPLOS, ISCA
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture17 papers
- hardware9 papers
- accelerators4 papers
- hardware accelerators0 papers
- designs0 papers
Paper list
From the lab homepage.
202627 papers
- IEEE JSSCA 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models
- IEEE TVLSIAlgorithm-Hardware Co-Design of Digital Compute-in-Memory Architecture Supporting Flexible and Temporal N:M Sparsity
- ASP-DACBoosting Scalability and Performance: Macro Placement for Flexible 3D-Stacked ML Accelerators
- ICSClosing the Efficiency Gap: AI Datacenter Co-design Roadmap for Scalable Training of LLMs
- ASPLOS (T1)Compositional AI Beyond LLMs: System Implications of Neuro-Symbolic-Probabilistic Architectures
- ACM TECSCross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration
- ICCAD (T1)Demystifying AI Platform Design for Distributed Inference of Next-Generation LLM Models
- MICRO (T1)Demystifying the Cost Versus Benefits of Sparse Large Language Model Acceleration
- SIGCOMM (T1)DynamoServe: A Distributed Tiered Memory System for Multi-tenant LLM Serving
- DAC (T1)Enabling AI ASICs for Zero Knowledge Proof
- ISPASSEvaluating Cross-Architecture Performance Modeling of Distributed ML Workloads Using StableHLO
- DATEFortiSky: Enhancing Adversarial and Bit-Error Robustness for Efficient and Secure Autonomous Systems
202525 papers
- ISLPEDAccelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Accelerator
- MLSys (T1)AI Metropolis: Scaling Large Language Model-based Multi-Agent Simulation with Out-of-order Execution
- DATEAIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Representations
- DATEAxon: A Novel Systolic Array Architecture for Improved Energy-Efficient GeMM and Conv Operation with On-Chip im2col
- IPDPSCELLO: Co-designing Schedule and Hybrid Implicit/Explicit Buffer for Complex Tensor Reuse
- MICRO (T1)Characterizing the Efficiency of Distributed Training: A Power, Performance, and Thermal Perspective
- HPCA (T1)CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
- NeuSEfficient Processing of Neuro-Symbolic AI: A Tutorial and Cross-Layer Co-Design Case Study
- MLSys (T1)Enabling Unstructured Sparse Acceleration on Structured Sparse Accelerators
- ISPASSExploring Constrained Dataflow Accelerators for Real-Time Multi-Task Multi-Model ML Workloads
- MLSys (T1)FlexInfer: Flexible LLM Inference with CPU Computations
- ISCA (T1)FRED: A Wafer-scale Fabric for 3D Parallel DNN Training
202416 papers
- DAC (T1)Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
- ECCV (T1)CLAMP-ViT: Contrastive Data-Free Learning for Adaptive Post-Training Quantization of ViTs
- IA³ @ SCEnhancing Scalability and Performance in Influence Maximization with Optimized Parallel Processing
- ISCA (T1)FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
- ENLSP@NeurIPSGEAR: An Efficient Error Reduction Framework for KV Cache Compression in LLM Inference
- DATEH3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations
- ISPASSLeveraging Memory Expansion to Accelerate Large-Scale DL Training
- ISPASSLIBRA: Enabling Workload-aware Multi-dimensional Network Topology Optimization for Distributed Training of Large AI Models
- IEEE T-RadarReal-time Digital RF Emulation – II: A Near-Memory Custom Accelerator
- MLSys (T1)SmartPAF: Accurate Low-Degree Polynomial Approximation of Non-polynomial Operators for Fast Private Inference in Homomorphic Encryption
- MICRO (T1)TACOS: Topology-Aware Collective Algorithm Synthesizer for Distributed Machine Learning
- ICCAD (T1)Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems
202319 papers
- RadarConfA High Performance Computing Architecture for Real-Time Digital Emulation of RF Interactions
- DATEAIRCHITECT: Automating Hardware Architecture and Mapping Optimization
- ISPASSASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale
- ISPASSCharacterization of Data Compression in Datacenters
- AAAI (T1)Efficient Distributed Inference of Deep Neural Networks via Restructuring and Pruning
- ASPLOS (T1)FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks
- ASPLOS (T1)Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
- IMSFPGA-Based High-Performance Real-Time Emulation of Radar System using Direct Path Compute Model
- MICRO (T1)Hardware-Software Co-Design for Real-Time Latency-Accuracy Navigation in Tiny Machine Learning Applications
- IEEE CALMitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping
- IEEE TVLSIOn Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs
- DATEProteus: HLS-based NoC Generator and Simulator
Where alumni went
Alumni are not listed on the lab homepage.
Apply to Georgia TechFall 2027
Georgia Tech Computer Science PhD
- Round
- Single round
- Opens
- —
- GRE
- optional
- English
- TOEFL/IELTS
- Fee
- See program page
Not yet confirmed for this intake.
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