Xunzhao Yin
ZJU100 Young Professor
Designs circuits and systems built on emerging devices and new computing models, such as in-memory computing for AI.
Xunzhao Yin's lab at Zhejiang works on accelerators, chips & architecture. 60 papers since 2023, 15 at top venues, mostly DAC and ICCAD. Applications close .
At a glance
- papers, 2023–2026
- 16/ year
- at T1 venues
- 25%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 7 papers2026 · T1 0 · collecting
- 17 papers2025 · T1 7
- 22 papers2024 · T1 7
- 14 papers2023 · T1 1
T1 venuesOtherVenues: DAC, ICCAD
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture6 papers
- in-memory computing3 papers
- emerging1 paper
- emerging devices0 papers
- built0 papers
Paper list
From DBLP.
20267 papers
- ISQEDAutoBeaVer: Automating Behavioral Modeling and Verification in Library Characterization with LLM Agents (opens in a new tab)
- ASP-DACCDACiM: A Charge-Domain Compute-in-Memory Macro for FP/INT MAC Operations with Reconfigurable Capacitor Digital-Analog-Converter (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable Memories (opens in a new tab)
- IEEE Trans. ComputersFeFET-Based Analog In-Memory Computing With Inherent Shift-and-Add Capability (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.Machine Learning-Assisted VCD Processing for Accelerated Dynamic Voltage Drop Analysis (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.ZlibBoost: An Efficient and Flexible Open-Source Framework for Standard Cell Characterization (opens in a new tab)
202517 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Homogeneous FeFET-Based Time-Domain Compute-in-Memory Fabric for Matrix-Vector Multiplication and Associative Search (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search (opens in a new tab)
- ICCAD (T1)Accelerating Electro-Thermal Co-Analysis via Coarse-to-Fine Physics-Informed Neural Networks (opens in a new tab)
- Integr.ANAS: Software-hardware co-design of approximate neural network accelerators via neural architecture search (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.CSA-CiM: Enhancing Multifunctional Computing-in-Memory With Configurable Sense Amplifiers (opens in a new tab)
- DAC (T1)Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems (opens in a new tab)
- ICCAD (T1)FACAM: Design and Optimization of A Compact Energy Efficient FeFET-Based Analog Content Addressable Memory (opens in a new tab)
- DAC (T1)FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Fast Machine-Learning-Driven Supply Noise-Aware Macromodeling for High-Speed Nonlinear Drivers (opens in a new tab)
- DAC (T1)FeKAN: Efficient Kolmogorov-Arnold Networks Accelerator Using FeFET-based CAM and LUT (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.Ferroelectric Compute-in-Memory Framework for Solving Pure and Mixed Strategy Nash Equilibrium (opens in a new tab)
- IEEE Trans. ComputersHigh-Performance In-Memory Bayesian Inference With Multi-Bit Ferroelectric FET (opens in a new tab)
202422 papers
- DATEA FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation (opens in a new tab)
- MLCADA Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits (opens in a new tab)
- MLCADAutomated C/C++ Program Repair for High-Level Synthesis via Large Language Models (opens in a new tab)
- ICCAD (T1)BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks (opens in a new tab)
- DAC (T1)C-Nash: A Novel Ferroelectric Computing-in-Memory Architecture for Solving Mixed Strategy Nash Equilibrium (opens in a new tab)
- DATEClass-Aware Pruning for Efficient Neural Networks (opens in a new tab)
- DATEComputational and Storage Efficient Quadratic Neurons for Deep Neural Networks (opens in a new tab)
- ASPDACConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out Dataflow (opens in a new tab)
- IEEE Trans. Circuits Syst. Artif. Intell.EncodingNet: A Novel Encoding-Based MAC Design for Efficient Neural Network Acceleration (opens in a new tab)
- DAC (T1)Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability (opens in a new tab)
- IEEE Trans. Very Large Scale Integr. Syst.Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow (opens in a new tab)
202314 papers
- IEEE Des. TestA DVFS Design and Simulation Framework Using Machine Learning Models (opens in a new tab)
- IEEE Trans. Circuits Syst. I Regul. Pap.A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance (opens in a new tab)
- Adv. Intell. Syst.An Ultracompact Single-Ferroelectric Field-Effect Transistor Binary and Multibit Associative Search Engine (opens in a new tab)
- ASP-DACApproximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency (opens in a new tab)
- Sci. China Inf. Sci.Breaking the energy-efficiency barriers for smart sensing applications with "Sensing with Computing" architectures (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.FeFET-Based In-Memory Hyperdimensional Encoding Design (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search (opens in a new tab)
- J. Comput. Sci. Technol.LMM: A Fixed-Point Linear Mapping Based Approximate Multiplier for IoT (opens in a new tab)
- ESSDERCReconfigurable ferroelectric hafnium oxide FeFET fabricated in 28 nm CMOS technology for mmWave applications (opens in a new tab)
- ICCAD (T1)SEE-MCAM: Scalable Multi-Bit FeFET Content Addressable Memories for Energy Efficient Associative Search (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to ZhejiangFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- Per ZJU language requirements
- Fee
- RMB 800
Not yet confirmed for this intake.
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