Yufei Ma
长聘副教授
Designs energy-efficient AI accelerator chips through circuit, architecture and algorithm-hardware co-design.
Yufei Ma's lab at Peking works on accelerators, chips & architecture and efficient training & inference. 23 papers since 2023, 7 at top venues, mostly DAC and CVPR. Applications close .
At a glance
- papers, 2023–2026
- 6/ year
- at T1 venues
- 30%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 0 papers2026 · T1 0 · collecting
- 8 papers2025 · T1 4
- 9 papers2024 · T1 2
- 6 papers2023 · T1 1
T1 venuesOtherVenues: DAC, CVPR, ICCAD
Research focuspaper titles that use each topic's words
- accelerator6 papers
- Accelerators, chips & architecture4 papers
- Efficient training & inference1 paper
- circuit0 papers
- algorithm-hardware0 papers
Paper list
From the lab homepage.
20258 papers
- ISSCC13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction
- ICCAD (T1)3D-MoE: Accelerating Multi-Expert Activated LLMs on 3D In/Near-Memory Computing Architecture via Hybrid Parallelism
- DAC (T1)3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs
- DAC (T1)3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference
- JSSCA 22-nm Delta–Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing
- JSSCA 22-nm Residual Spiking Neural Network Chip Based on Sparsity-Adaptive In-Memory Computing and a Spike-Driven Architecture
- CVPR (T1)Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition
- TCAS-IQuartet: A Digital Compute-in-Memory Versatile AI Accelerator With Heterogeneous Tensor Engines and Off-Chip-Less Dataflow
20249 papers
- ISSCC30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing
- SSC-LA 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations
- VLSI-CA Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup
- DAC (T1)AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration
- DAC (T1)An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology
- TCAS-IDCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network
- CICCQuartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow
- CICCS2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications
- TCAS-ISparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network
20236 papers
- ISSCC7.8 A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing
- CICCA 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology
- DAC (T1)A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware
- ISLPEDDCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler
- TCAS-IHighlight of 2023 August Issue
- ASP-DACRIMAC: An Array-level ADC/DAC-free ReRAM-based In-Memory DNN Processor with Analog Cache and Computation
Where alumni went
Alumni are not listed on the lab homepage.
Apply to PekingFall 2027
Computer Science PhD (international applicants)
- Round
- Main
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
Similar labsnearest by research summary
- USNYU
Sai Qian Zhang
- Accelerators, chips & architecture
- CNSJTU
Li Jiang
- Accelerators, chips & architecture
- GBImperial
George Constantinides
- Accelerators, chips & architecture
- GBCambridge
Robert Mullins
- Accelerators, chips & architecture
- CNSJTU
Honglan Jiang
- Accelerators, chips & architecture
- CHETH Zurich
Torsten Hoefler
- Distributed, cloud & edge systems
Your notes
Save this lab to keep notes.
Data
Some numbers could not be verified:
- The member list could not be found on the lab site.
- The alumni list could not be found on the lab site.
- Collected
- Verified
- Papers
- The lab homepage
- Members
- Not collected
- Alumni
- Not collected
Tiers are venue classifications, not lab rankings.
Pekingcloses