Li Jiang
Professor
Works on AI infrastructure in computer architecture, including AI processor and accelerator design, inference compilers and processing-in-memory architectures.
Li Jiang's lab at SJTU works on accelerators, chips & architecture and efficient training & inference. 18 papers since 2023, 11 at top venues, mostly ASPLOS and DAC. Applications close .
At a glance
- papers, 2023–2026
- 5/ year
- at T1 venues
- 61%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom the lab homepage, 2023–2026
- 8 papers2026 · T1 4 · collecting
- 10 papers2025 · T1 7
- 0 papers2024 · T1 0
- 0 papers2023 · T1 0
T1 venuesOtherVenues: ASPLOS, DAC, HPCA, AAAI, ISCA
Research focuspaper titles that use each topic's words
- Efficient training & inference6 papers
- accelerator3 papers
- Accelerators, chips & architecture1 paper
- processor0 papers
- compilers0 papers
Paper list
From the lab homepage.
20268 papers
- ASPLOS (T1)AGS: Accelerating 3D Gaussian Splatting SLAM via CODEC-Assisted Frame Covisibility Detection
- PPoPPBEEMS: Boosting Machine Vision Efficiency via Computation Graph-Based Memory Smoothing
- ASP-DACBLADE: Boosting LLM Decoding's Communication Efficiency in DRAM-based PIM
- ASPLOS (T1)EARTH: An Efficient MoE Accelerator with Entropy-Aware Speculative Prefetch and Result Reuse
- HPCA (T1)ORANGE: Exploring Ockham's Razor for Neural Rendering by Accelerating 3DGS on NPUs with GEMM-Friendly Blending and Balanced Workloads
- AAAI (T1)SpecQuant: Spectral Decomposition and Adaptive Truncation for Ultra-Low-Bit LLMs Quantization
- ASP-DACTFLOP: Towards Energy-Efficient LLM Inference An FPGA-Affinity Accelerator with Unified LUT-based OPtimization
- ASP-DACWhen Low-Rank Meets Mixed-Precision: Training-Free Joint Compression for Efficient LLM Inference
202510 papers
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsA Sub-10 μs In-Memory-Search Collision Detection Accelerator Based on RRAM-TCAMs
- DAC (T1)ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid Workloads
- ASPLOS (T1)ASDR: Exploiting Adaptive Sampling and Data Reuse for CIM-based Instant Neural Rendering
- ACM Transactions on Architecture and Code OptimizationAttack and Defense: Enhancing Robustness of Binary Hyper-Dimensional Computing
- DAC (T1)BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
- HPCA (T1)CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels
- ISCA (T1)FATE: Boosting the Performance of Hyper-Dimensional Computing Intelligence with Flexible Numerical DAta TypE
- HPCA (T1)GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support
- DAC (T1)MILLION: MasterIng Long-Context LLM Inference Via Outlier-Immunized KV Product QuaNtization
- ACM Transactions on Design Automation of Electronic SystemsSTCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
- Round
- Self-funded
- Opens
- —
- GRE
- See program page
- English
- See program page
- Fee
- See program page
Not yet confirmed for this intake.
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Data
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- The member list could not be found on the lab site.
- The alumni list could not be found on the lab site.
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