CNShanghai Jiao Tong UniversitySchool of Integrated Circuits (Information and Electronic Engineering)
Naifeng Jing
研究员
Works on high-performance AI chips, GPGPU architecture and compute-in-memory.
Naifeng Jing's lab at SJTU works on accelerators, chips & architecture. 58 papers since 2023, 13 at top venues, mostly DAC and ISCA. Applications close .
At a glance
- papers, 2023–2026
- 15/ year
- at T1 venues
- 22%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 9 papers2026 · T1 2 · collecting
- 17 papers2025 · T1 7
- 17 papers2024 · T1 3
- 15 papers2023 · T1 1
T1 venuesOtherVenues: DAC, ISCA, ASPLOS, Expert Systems with Applications, HPCA
Research focuspaper titles that use each topic's words
- Accelerators, chips & architecture14 papers
- architecture9 papers
- high-performance1 paper
- chips1 paper
- compute-in-memory0 papers
Paper list
From DBLP.
20269 papers
- CICCA 51.19 mm2, 4 TB/s bandwidth 3D Logic-on-SRAM Stacking CGRA Chip (opens in a new tab)
- ASPLOS (T1)AGS: Accelerating 3D Gaussian Splatting SLAM via CODEC-Assisted Frame Covisibility Detection (opens in a new tab)
- ISCA (T1)CHIME: A Case for Efficient Long-Context Attention-FC Disaggregated Inference with DIMM-PIM (opens in a new tab)
- ACM Trans. Archit. Code Optim.GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.HARMONY: A Hardware-Aware Mapping and Optimizing Framework for Computing-in-Memory Accelerators (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture (opens in a new tab)
- Microelectron. J.Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study (opens in a new tab)
- Microelectron. J.TSE-CAM: A configurable approximate multiplier for DVFS systems via two-stage structural evolution (opens in a new tab)
- ASP-DACViper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption (opens in a new tab)
202517 papers
- IEEE Trans. Very Large Scale Integr. Syst.A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip (opens in a new tab)
- HPCA (T1)AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing (opens in a new tab)
- DAC (T1)AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System (opens in a new tab)
- IEEE J. Emerg. Sel. Topics Circuits Syst.Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System (opens in a new tab)
- ACM Trans. Archit. Code Optim.GCNTrain+: A Versatile and Efficient Accelerator for Graph Convolutional Neural Network Training (opens in a new tab)
- MICRO (T1)HEAT: NPU-NDP HEterogeneous Architecture for Transformer-Empowered Graph Neural Networks (opens in a new tab)
- DATEHEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler (opens in a new tab)
- ISCA (T1)LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators (opens in a new tab)
- ASP-DACMDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing (opens in a new tab)
- DAC (T1)MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization (opens in a new tab)
202417 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator (opens in a new tab)
- ISCASA 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture (opens in a new tab)
- ISCASA Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm (opens in a new tab)
- Expert Systems with ApplicationsA novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance (opens in a new tab)
- ASPDACBridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture (opens in a new tab)
- ASPLOS (T1)CMC: Video Transformer Acceleration via CODEC Assisted Matrix Condensing (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating (opens in a new tab)
- ICCDEarly: An Importance-Aware Early Firing and Exit for SNN Acceleration (opens in a new tab)
- DAC (T1)Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators (opens in a new tab)
- ACM Trans. Archit. Code Optim.Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Janus: A Flexible Processing-in-Memory Graph Accelerator Toward Sparsity (opens in a new tab)
202315 papers
- IEEE Trans. Parallel Distributed Syst.A Point Cloud Video Recognition Acceleration Framework Based on Tempo-Spatial Information (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration (opens in a new tab)
- ICCDACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors (opens in a new tab)
- DAC (T1)AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity (opens in a new tab)
- ASP-DACAn Efficient near-Bank Processing Architecture for Personalized Recommendation System (opens in a new tab)
- ASICONAn NoC-based CNN Accelerator for Edge Computing (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.E2-VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition (opens in a new tab)
- Integr.Exploiting bit sparsity in both activation and weight in neural networks accelerators (opens in a new tab)
- ASICONHigh-Performance Genomic Analysis Heterogeneous System Using OpenCL (opens in a new tab)
- ICCDHyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model (opens in a new tab)
- FPLPipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture (opens in a new tab)
- DATEPRADA: Point Cloud Recognition Acceleration via Dynamic Approximation (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to SJTUFall 2027
Computer Science PhD (international applicants)
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- Self-funded
- Opens
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- GRE
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- English
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Not yet confirmed for this intake.
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