Andrew B. Kahng
Distinguished Professor
Researches VLSI physical design and the design-manufacturing interface, applying machine learning to chip design automation.
Andrew B. Kahng's lab at UCSD works on accelerators, chips & architecture and interfaces & interaction techniques. 43 papers since 2023, 9 at top venues, mostly ICCAD and AAAI. Applications close .
At a glance
- papers, 2023–2026
- 11/ year
- at T1 venues
- 21%
- PhD students
- —
- MS students
- —
- alumni listed
- —
Papers by yearfrom DBLP, 2023–2026
- 8 papers2026 · T1 0 · collecting
- 9 papers2025 · T1 2
- 17 papers2024 · T1 4
- 9 papers2023 · T1 3
T1 venuesOtherVenues: ICCAD, AAAI, DAC
Research focuspaper titles that use each topic's words
- design12 papers
- Accelerators, chips & architecture4 papers
- vlsi4 papers
- Interfaces & interaction techniques0 papers
- applying machine0 papers
Paper list
From DBLP.
20268 papers
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.An Updated Assessment of Reinforcement Learning for Macro Placement (opens in a new tab)
- ASP-DACAu-MEDAL: Adaptable Grid Router with Metal Edge Detection And Layer Integration (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.ChipletPart: Cost-Aware Partitioning for 2.5D Systems (opens in a new tab)
- ISPDInvited: Agentic AI for Physical Design R&D: Status and Prospects (opens in a new tab)
- ISPDInvited: Post-Placement Buffering and Sizing Contest (opens in a new tab)
- ISPDInvited: The Many PD Faces of Professor Jens Lienig (opens in a new tab)
- ISPDInvited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research (opens in a new tab)
- ISCASLSMC Meets GPU Acceleration: Scalable and High-Quality Multi-Row Detailed Placement (opens in a new tab)
20259 papers
- FCCMA Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators (opens in a new tab)
- ICCAD (T1)Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem (opens in a new tab)
- ISPDInvited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research (opens in a new tab)
- MLCADORFS-agent: Tool-Using Agents for Chip Design Optimization (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators (opens in a new tab)
- MLCADRecursive Learning-Based Virtual Buffering for Analytical Global Placement (opens in a new tab)
- ICCAD (T1)SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing (opens in a new tab)
- ASP-DACUse Cases and Deployment of ML in IC Physical Design (opens in a new tab)
202417 papers
- ACM Great Lakes Symposium on VLSIA Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks (opens in a new tab)
- DATEImprovement of Mixed Track - Height Standard-Cell Placement (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning (opens in a new tab)
- AAAI (T1)NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem (opens in a new tab)
- VTSOpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education (opens in a new tab)
- ISPDPanel Statement: EDA Needs at Advanced Technology Nodes (opens in a new tab)
- ICCAD (T1)Placement Tomography-Based Routing Blockage Generation for DRV Hotspot Mitigation (opens in a new tab)
- DAC (T1)PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs (opens in a new tab)
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement (opens in a new tab)
20239 papers
- ISQEDAn Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing (opens in a new tab)
- ICCAD (T1)An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design (opens in a new tab)
- ISPDAssessment of Reinforcement Learning for Macro Placement (opens in a new tab)
- ACM Trans. Design Autom. Electr. Syst.DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs (opens in a new tab)
- SLIPGear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration (opens in a new tab)
- ICCAD (T1)Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research (opens in a new tab)
- ICCAD (T1)Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff (opens in a new tab)
- IEEE Des. TestMachine Learning for CAD/EDA: The Road Ahead (opens in a new tab)
- MLCADThe 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results (opens in a new tab)
Where alumni went
Alumni are not listed on the lab homepage.
Apply to UCSDFall 2027
UCSD CSE Computer Science PhD
- Round
- Single round
- Opens
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- GRE
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- English
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- Fee
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Not yet confirmed for this intake.
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Data
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